A 500 MHz low offset fully differential latched comparator

Naghavi, Saeed; Sharifi, Niloofar; Nematzadeh, Mozhdeh; Khanshan, Tohid Moradi; Abrishamifar, Adib; Kuzekanani, Zia Daei; Sobhi, Jafar

doi:10.1007/s10470-017-0998-z

Analog Integr Circ Sig Process

2017

DOI: 10.1007/s10470-017-0998-z

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A 500 MHz low offset fully differential latched comparator

Saeed Naghavi

Niloofar Sharifi

Mozhdeh Nematzadeh

et al.

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Cited by 2 publications

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“…However, in order to improve the speed/accuracy trade-off of low-power ADCs, the improvement in the speed performance and power consumption of the double-tail dynamic comparators has drawn the most attention of the analogue integrated circuits designers [11][12][13][14][15]. In the recent years, various approaches have been discussed in [16][17][18][19][20][21][22][23], to improve the input offset performance of the comparators. Moreover, the reduction of the input-referred noise has been addressed in [24,25].…”

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confidence: 99%

An energy‐efficient dynamic comparator in Carbon Nanotube Field Effect Transistor technology for successive approximation register ADC applications

Mahmoodian

Dolatshahi

Zanjani

et al. 2022

IET Circuits, Devices & Syst

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In this paper, a latch‐based energy‐efficient dynamic comparator is presented in Carbon Nanotube Field Effect Transistor (CNTFET) technology. The proposed comparator consists of two main stages: pre‐amplifier and latch. The latch stage is designed for the main purpose of low‐power consumption and high‐speed performances. The proposed speed‐up technique for the latch structure controls the threshold voltage (Vth) of the cross‐coupled inverters. So, the delay of the latch stage decreases and consequently, the overall delay of the comparator circuit is also reduced up to 19.4% while the maximum speed performance of the proposed comparator increases by 54% compared to the conventional double‐tail dynamic comparator. Additionally, the use of the proposed distinctive structure for the tail transistors in the latch stage, leads to more than 11% reduction in the energy per conversion of the proposed circuit compared to the conventional double‐tail dynamic comparator. To verify the circuit performances, the comparator circuit is simulated in HSPICE using 32 nm CNTFET Stanford model technology parameters. The simulation results show that the proposed comparator with the proposed speed‐up approach can operate up to 14.2 GHz with a sensitivity of 30 μV at the supply voltage of 1 V, while consumes only 42.38 μW of power. Therefore, the proposed comparator can be used in high‐resolution (up to 12 bit) and high‐speed low‐power analogue‐to‐digital converter applications. Moreover, the effects of the non‐ideal fabrication process (including the pitch and the threshold voltage variations), supply voltage and temperature variations are investigated in this work. Monte‐Carlo analysis shows that the standard deviation of the offset voltage is approximately 1.24 mV. Finally, the kickback noise of the proposed comparator is obtained as 80 μV, which shows the proper performance of the proposed comparator circuit in comparison with other reported designs.

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mentioning

confidence: 99%

An energy‐efficient dynamic comparator in Carbon Nanotube Field Effect Transistor technology for successive approximation register ADC applications

Mahmoodian

Dolatshahi

Zanjani

et al. 2022

IET Circuits, Devices & Syst

View full text Add to dashboard Cite

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A 0.2-V 1.2 nW 1-KS/s SAR ADC with a novel comparator structure for biomedical applications

et al. 2023

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A 500 MHz low offset fully differential latched comparator

Cited by 2 publications

References 17 publications

An energy‐efficient dynamic comparator in Carbon Nanotube Field Effect Transistor technology for successive approximation register ADC applications

An energy‐efficient dynamic comparator in Carbon Nanotube Field Effect Transistor technology for successive approximation register ADC applications

A 0.2-V 1.2 nW 1-KS/s SAR ADC with a novel comparator structure for biomedical applications

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