A 500-MHz multi-banked compilable DRAM macro with direct write and programmable pipelining

Barth, J.; Anand, D.; Burns, Steven; Dreibelbis, J.; Fifield, J.A.; Gorman, K.; Nelms, M.; Nelson, Erik; Paparelli, A.; Pomichter, G.; Pontius, D.; Sliva, S.

doi:10.1109/jssc.2004.838001

Cited by 16 publications

(3 citation statements)

References 4 publications

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“…For LP-DRAM, we obtain technology data by extrapolating published data of 180/130/90/65nm LP-DRAM processes [12,38]. For COMM-DRAM, we obtain technology data by using projections from the ITRS and other sources [3,23,24].…”

Section: Dram Modelingmentioning

confidence: 99%

A Comprehensive Memory Modeling Tool and Its Application to the Design and Analysis of Future Memory Hierarchies

Thoziyoor

Ahn

Monchiero

et al. 2008

2008 International Symposium on Computer Architecture

173

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In this paper we introduce CACTI-D, a significant enhancement of CACTI 5.0. CACTI-D adds support for modeling of commodity DRAM technology and support for main memory DRAM chip organization. CACTI-D enables modeling of the complete memory hierarchy with consistent models all the way from SRAM based L1 caches through main memory DRAMs on DIMMs.We illustrate the potential applicability of CACTI-D in the design and analysis of future memory hierarchies by carrying out a last level cache study for a multicore multithreaded architecture at the 32nm technology node. In this study we use CACTI-D to model all components of the memory hierarchy including L1, L2, last level SRAM, logicprocess based DRAM or commodity DRAM L3 caches, and main memory DRAM chips. We carry out architectural simulation using benchmarks with large data sets and present results of their execution time, breakdown of power in the memory hierarchy, and system energy-delay product for the different system configurations. We find that commodity DRAM technology is most attractive for stacked last level caches, with significantly lower energy-delay products.

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Section: Dram Modelingmentioning

confidence: 99%

A Comprehensive Memory Modeling Tool and Its Application to the Design and Analysis of Future Memory Hierarchies

Thoziyoor

Ahn

Monchiero

et al. 2008

2008 International Symposium on Computer Architecture

173

View full text Add to dashboard Cite

show abstract

“…To achieve high memory bandwidth, various techniques such as widening input/output pins [1], shrinking the unit array size [2], and performing a read operation and a write operation concurrently [3,4] have been reported. However, these embedded DRAM macros incur considerable area penalty to obtain high memory bandwidth.…”

mentioning

confidence: 99%

“…To increase the repair efficiency, steering switch redundancy systems have been reported [1,5]. The steering switches on the data lines are shifted according to the input address.…”

mentioning

confidence: 99%

An 833MHz Pseudo-Two-Port Embedded DRAM for Graphics Applications

Mariko

Hitoshi

Nagai

et al. 2008

2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers

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Embedded DRAMs have superior features for applications that require very high memory bandwidth, such as graphics and multimedia. To achieve high memory bandwidth, various techniques such as widening input/output pins [1], shrinking the unit array size [2], and performing a read operation and a write operation concurrently [3,4] have been reported. However, these embedded DRAM macros incur considerable area penalty to obtain high memory bandwidth. Figure 14.4.1 shows the cell efficiency versus the memory bandwidth of the macros reported recently. Among the techniques for achieving high bandwidth, the concurrent read/write operation is a very effective method in performing a read-modify-write function and a double-buffer function for the graphics applications. We describe a pseudo-two-port embedded DRAM macro that performs concurrent read/write operations at high frequency without sacrificing cell efficiency. To accomplish this, we introduce, a read/write cross-point switch circuit (RWCC) and distributed steering redundancy switches (DSRS). A 32Mb macro is characterized via a test-chip fabricated in a 65nm embedded DRAM process. We confirm page-mode operating frequency of 833MHz at 1.2V.In the previous work [3,4], in order to realize the concurrent read/write operation, the data lines connecting sense amplifies and input/output circuits are separated into read path and write path. Since this requires additional switches for each sense amplifier, the area overhead of the sense amplifier region is considerable. This decreases the cell efficiency of the macros.Our pseudo-two-port embedded DRAM macro performs a read operation and a write operation concurrently in two different banks. Figure 14.4.2 shows the block diagram of the DRAM macro. A read/write cross-point switch circuit (RWCC) is placed between two adjacent banks. The RWCC consists of 2 nd sense amplifiers (R), write buffers (W), and data path switches. Local read/write data lines (LRWD) are bidirectional data lines in a bank, and global data lines are separated into read path (GRD) and write path (GWD). The RWCC controls connections between GRD/GWD and LRWD according to the address for bank selection and the read/write commands. In this way, the read data from a bank do not collide with the write data to the other bank on the data path. Therefore, the concurrent read/write operation can be performed in different two banks. Since bidirectional data lines in a bank are used in a similar way to a conventional single-port DRAM, the area penalty for the sense amplifier region is eliminated. The macro area overhead for the concurrent read/write operation is less than 1%. Each of the two input ports has a full set of inputs for the address and the control signals for read, write, active, and precharge. The addresses and the commands are independently asserted for each port. Only simultaneous read and simultaneous write command inputs from the two ports are prohibited. During continuous read operations in a bank, write commands are asserted independently to another b...

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Embedded Memory Architecture for Low-Power Application Processor

Yoo¹,

Kim²

2009

Integrated Circuits and Systems

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A 500-MHz multi-banked compilable DRAM macro with direct write and programmable pipelining

Cited by 16 publications

References 4 publications

A Comprehensive Memory Modeling Tool and Its Application to the Design and Analysis of Future Memory Hierarchies

A Comprehensive Memory Modeling Tool and Its Application to the Design and Analysis of Future Memory Hierarchies

An 833MHz Pseudo-Two-Port Embedded DRAM for Graphics Applications

Embedded Memory Architecture for Low-Power Application Processor

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