A 500 ps 32 × 8 register file implemented in GaAs/AlGaAs HBTs [F-RISC/G processor]

Abstract

A high speed register file has been designed that is wellsuited for achieving the speed potential of a fast but yieldlimited technology such a5 GaAs/AlGaAs HBT. Descriptions of address driver, write, and threshold voltage generator circuits developed are presented. The test strategy utilizes two Linear Feedback Shift, Registers (LFSRs) to provide address and data patterns to the register file. A match circuit verifies valid memory function and indicates read access time. The test results indicaie a read access time of 500 ps.

Low Power, High-Speed ADCs and Digital Circuits for SKA

“…Logic gates that are based on current mode logic (CML) and emitter coupled logic (ECL) circuits are an ideal choice for applications with high clock rates Nah et al (1993); Montgomery et al (1991); Hafizi et al (1992); Yinger et al (1993). CMOS technology is limited in high precision applications, such as ADCs due to the stringent requirement of device matching.…”