A wideband thin-flm Wafer Scale Hybrid Package (WSEP) or multi-chip module (MCM) will be used to interconnect the chips of a high-perfownonce RISC architecture developed at Rensselaer. This architecture is being implemented using GaAs/AlGaAs Heterojunction Bipolar hnsistors (HBTs) and triple-level differential current-mode logic. Because of high power consumption f i l d limitaiions of the HBT technology, the processor is partitioned into multiple chips. These chips must be connected using lines capable of handling the fasi rise-time signals. Also, the multi-chip module must contain integrated b p s capacitors and termination resistors.
A standard cell library for implementing Rensselaer's Fast Reduced Instruction Set Computer (F-RISC/G) project with Rockwell's AlGaAs/GaAs Heterojunction Bipolar Transistor (HBT) technology is presented. The processor is targeted at an instruction cycle time of 1.0 ns. Difjerential Current Mode Logic (CML) is used, and unloaded gate delays are 15-20 P S .
Abstract-A digital voltage-controlled oscillator (VCO) is described which uses frequency multiplication and division to achieve very wide bandwidth. The VCO uses current-mode logic and does not require reactive elements such as inductors, capacitors or varactors. A novel, fully symmetric exclusive-OR (XOR) circuit was developed which uses product pairs and emitter-coupled logic. To achieve the highest performance possible, the critical path is symmetric and special physical design techniques were developed to promote matched-capacitance. The maximum measured frequency was 13.66 GHz. The chip occupies 1.9 mm 2 1.6 mm and dissipates 2.45 W at a supply voltage of 06.0 V. With a measured frequency range from 1.25 to 13.66 GHz, this circuit has the widest bandwidth reported in the literature for any VCO, digital or analog.
A high speed register file has been designed that is wellsuited for achieving the speed potential of a fast but yieldlimited technology such a5 GaAs/AlGaAs HBT. Descriptions of address driver, write, and threshold voltage generator circuits developed are presented. The test strategy utilizes two Linear Feedback Shift, Registers (LFSRs) to provide address and data patterns to the register file. A match circuit verifies valid memory function and indicates read access time. The test results indicaie a read access time of 500 ps.
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