Wideband wafer-scale interconnections in a wafer scale hybrid package for a 1000 MIPS highly pipelined GaAs/AlGaAs HBT RISC

Philhower, R.; Etten, J.S. Van; Dabral, S.; Nah, Kyung-Suc; Greub, H.; McDonald, J. F.

doi:10.1109/icwsi.1992.171805

Cited by 4 publications

(4 citation statements)

References 10 publications

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“…The F-RISG/G processor uses small chips on a multichip module (MCM) [3]. With a cycle time of 1 ns and a clock frequency of 2 GHz, the distribution of clock signals to all chips on the MCM is one of the most critical aspects of the design.…”

Section: Introductionmentioning

confidence: 99%

A very wide bandwidth digital VCO using quadrature frequency multiplication and division implemented in AlGaAs/GaAs HBT's

Campbell

Greub

Garg

et al. 1998

IEEE Trans. VLSI Syst.

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Abstract-A digital voltage-controlled oscillator (VCO) is described which uses frequency multiplication and division to achieve very wide bandwidth. The VCO uses current-mode logic and does not require reactive elements such as inductors, capacitors or varactors. A novel, fully symmetric exclusive-OR (XOR) circuit was developed which uses product pairs and emitter-coupled logic. To achieve the highest performance possible, the critical path is symmetric and special physical design techniques were developed to promote matched-capacitance. The maximum measured frequency was 13.66 GHz. The chip occupies 1.9 mm 2 1.6 mm and dissipates 2.45 W at a supply voltage of 06.0 V. With a measured frequency range from 1.25 to 13.66 GHz, this circuit has the widest bandwidth reported in the literature for any VCO, digital or analog.

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Section: Introductionmentioning

confidence: 99%

A very wide bandwidth digital VCO using quadrature frequency multiplication and division implemented in AlGaAs/GaAs HBT's

Campbell

Greub

Garg

et al. 1998

IEEE Trans. VLSI Syst.

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“…F-RISUG is a 32-bit RISC processor partitioned into four 8-bit datapath chips (DP), one instruction decoder chip(ID), one clock distribution and skew compensation chip (DSK), and primary and secondary level instruction and data caches [4]. The processor has a seven stage pipeline with a Harvard architecture (separate instruction and data caches) for storage.…”

Section: F-risc/g Systemmentioning

confidence: 99%

“…The processor has a seven stage pipeline with a Harvard architecture (separate instruction and data caches) for storage. The circuits are designed using three-level fully differential current-mode logic [4].…”

Section: F-risc/g Systemmentioning

confidence: 99%

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Thermal design of an advanced multichip module for a RISC processor

Garg

Sham²,

Greub³

et al.

Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computers and Processors

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4 9.1x7.0 12.8 2.0E5 51.2 16 8.Ox9.4 10.3 1.3E.5 164.8 2 8.Ox8.0 9.0 1.4E5 18.0 Multichip module (MCM) technology is attracting attention from designers who need high-speed interchip connections and a reliable package for their circuit applications. This technology is being applied to realize a I-ns cycle time 32-bit RISC processor, using 50 GHz AlGaAslGaAs heterojunction bipolar transistor (HBT) technology and triple-level fill-differential current mode logic (CML), at Rensselaer. The processor is partitioned into multiple chips due to the high power consumption and low integration level of the technology. There are several key challenges associated with this module. It has to provide high-bandwidth (S IO GHz) and high-density ( S 4 0 p pitch) interconnect, and dissipate nearly 250 W of power. Maximum heat flux on the MCM surface is 2 .Ox1 Os Wlm2. Poor heat conduction ability of GaAs chips make it tough to dissipate this heat. A methodology is developed to design a thermally stable module using a multilayer substrate with parylene as a low dielectric constant insulator, and fine pitch copper for high bandwidth lines. The design of the MCM and the thermal simulation results are presented. Controlla Clock Deskew Total

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A 16 GHz fast RISC engine using GaAs/AlGaAs and SiGe HBT technology

Steidl

Carlough²,

Ernest³

et al.

1997 Proceedings Second Annual IEEE International Conference on Innovative Systems in Silicon

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Wafer Scale Hybrid Packages (WSHP's) or Multichip Modules (MCM's) have provided a breakthrough in system packaging for high clock mte systems. Based on this technology a 2 GHz Fast RISC demonstration integer-only computational engine has been designed, and is submitted for fabrication [l]. This design involved use of Heterojunction Bipolar Transistors (HBT's) in the GaAdAlGaAs materials system. This paper reviews some of the schemes used in that design and shows how there are actually several paths using advanced GaAdAlGaAs and SiGe HE3T technology to create similar systems that can actually run 8 times faster. Some of the challenges facing the architect and chip designer are discussed.

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Wideband wafer-scale interconnections in a wafer scale hybrid package for a 1000 MIPS highly pipelined GaAs/AlGaAs HBT RISC

Cited by 4 publications

References 10 publications

A very wide bandwidth digital VCO using quadrature frequency multiplication and division implemented in AlGaAs/GaAs HBT's

A very wide bandwidth digital VCO using quadrature frequency multiplication and division implemented in AlGaAs/GaAs HBT's

Thermal design of an advanced multichip module for a RISC processor

A 16 GHz fast RISC engine using GaAs/AlGaAs and SiGe HBT technology

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