F-RISC/G: AlGaAs/GaAs HBT standard cell library

Nah, Kyung-Suc; Philhower, R.; Etten, J.S. Van; Simmons, Stephanie; Tsinker, Vadim; Loy, J.; Greub, H.; McDonald, J. F.

doi:10.1109/iccd.1991.139902

Cited by 6 publications

(4 citation statements)

References 4 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The outputs of the wired‐OR function are sent to the NOR gate in circuits, as shown in Fig. 3 a [28]. Another input of the NOR gate comes from the combination of A5 and A6.…”

Section: Circuit Design and Analysismentioning

confidence: 99%

Design of BiCMOS SRAMs for high‐speed SiGe applications

LeRoy

Clarke

Chu

et al. 2014

IET Circuits, Devices & Systems

View full text Add to dashboard Cite

This study documents the speeds of various SRAM buffer memories that are possible in a contemporary fast SiGe heterojunction bipolar transistor (HBT) BiCMOS process. An SRAM in a 0.13 µm HBT BiCMOS technology using current mode logic (CML)-style circuits serves as a basis for the discussion. This basic SRAM design features a CML decoder, CML word line driver, bipolar sense amplifier for achieving high speed and CMOS 6T memory cells for high density. The BiCMOS technology is especially useful for realising ultra-high-speed SRAMs for low level cache memory in high-clock rate computer systems, but when reorganised can also be utilised in analogue-to-digital converter (ADC) systems to store digitalised data. Speed and power tradeoffs can be made using different bias strategies, CML logic levels and different generations of SiGe HBTs. A demonstrated 128 kb SRAM macro consumes 2.7 W at 4 GHz using a −3.4 and −1.5 V supply voltage for the bipolar and CMOS circuits, respectively, and has dimensions of 3.5 mm × 3.6 mm by using IBM 8HP SiGe technology, which provides an HBT with a f T of 210 GHz. This macro can be integrated into large scale, ultra-wide bus SRAMs using heterogeneous silicon and 3D technology. Simulation indicates that with the next generation of SiGe HBTs, this SRAM macro can operate at 5 GHz, while consuming the same amount of power or alternatively consume 0.73 W, which is 73% less power consumption compared to 8HP, while operating with the same frequency of 4 GHz. Reorganising the memory for a 4 way-interleaved ADC, it can accept data written at 9.5 GS/s for 8HP designs, and 11.9 GS/s for 8XP designs.

show abstract

“…The outputs of the wired‐OR function are sent to the NOR gate in circuits, as shown in Fig. 3 a [28]. Another input of the NOR gate comes from the combination of A5 and A6.…”

Section: Circuit Design and Analysismentioning

confidence: 99%

Design of BiCMOS SRAMs for high‐speed SiGe applications

LeRoy

Clarke

Chu

et al. 2014

IET Circuits, Devices & Systems

View full text Add to dashboard Cite

show abstract

“…The logic circuitry is made from three-level current-mode logic (CML) gates wired dif-ferentiaIly [2]. The CML circuits have a loaded gate delay of 25 ps.…”

Section: Technologymentioning

confidence: 99%

A 500 ps 32 × 8 register file implemented in GaAs/AlGaAs HBTs [F-RISC/G processor]

Nah

Philhower²,

Greub³

et al.

15th Annual GaAs IC Symposium

Self Cite

View full text Add to dashboard Cite

A high speed register file has been designed that is wellsuited for achieving the speed potential of a fast but yieldlimited technology such a5 GaAs/AlGaAs HBT. Descriptions of address driver, write, and threshold voltage generator circuits developed are presented. The test strategy utilizes two Linear Feedback Shift, Registers (LFSRs) to provide address and data patterns to the register file. A match circuit verifies valid memory function and indicates read access time. The test results indicaie a read access time of 500 ps.

show abstract

“…This makes it possible to integrate these high speed chips to realize a high speed processor. This approach is being used to realize a 1-ns cycle time 32-bit fast-RISC (F-RISC/G) processor using 50 GHz AlGaAVGaAs HBT technology from Rockwell International with triple-level full differential CML [3]. The core chipset consists of twenty five chips as shown in Table I.…”

Section: Introductionmentioning

confidence: 99%

Thermal design of an advanced multichip module for a RISC processor

Garg

Sham²,

Greub³

et al.

Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computers and Processors

Self Cite

View full text Add to dashboard Cite

4 9.1x7.0 12.8 2.0E5 51.2 16 8.Ox9.4 10.3 1.3E.5 164.8 2 8.Ox8.0 9.0 1.4E5 18.0 Multichip module (MCM) technology is attracting attention from designers who need high-speed interchip connections and a reliable package for their circuit applications. This technology is being applied to realize a I-ns cycle time 32-bit RISC processor, using 50 GHz AlGaAslGaAs heterojunction bipolar transistor (HBT) technology and triple-level fill-differential current mode logic (CML), at Rensselaer. The processor is partitioned into multiple chips due to the high power consumption and low integration level of the technology. There are several key challenges associated with this module. It has to provide high-bandwidth (S IO GHz) and high-density ( S 4 0 p pitch) interconnect, and dissipate nearly 250 W of power. Maximum heat flux on the MCM surface is 2 .Ox1 Os Wlm2. Poor heat conduction ability of GaAs chips make it tough to dissipate this heat. A methodology is developed to design a thermally stable module using a multilayer substrate with parylene as a low dielectric constant insulator, and fine pitch copper for high bandwidth lines. The design of the MCM and the thermal simulation results are presented. Controlla Clock Deskew Total

show abstract

F-RISC/G: AlGaAs/GaAs HBT standard cell library

Cited by 6 publications

References 4 publications

Design of BiCMOS SRAMs for high‐speed SiGe applications

Design of BiCMOS SRAMs for high‐speed SiGe applications

A 500 ps 32 × 8 register file implemented in GaAs/AlGaAs HBTs [F-RISC/G processor]

Thermal design of an advanced multichip module for a RISC processor

Contact Info

Product

Resources

About