No abstract

A wideband thin-flm Wafer Scale Hybrid Package (WSEP) or multi-chip module (MCM) will be used to interconnect the chips of a high-perfownonce RISC architecture developed at Rensselaer. This architecture is being implemented using GaAs/AlGaAs Heterojunction Bipolar hnsistors (HBTs) and triple-level differential current-mode logic. Because of high power consumption f i l d limitaiions of the HBT technology, the processor is partitioned into multiple chips. These chips must be connected using lines capable of handling the fasi rise-time signals. Also, the multi-chip module must contain integrated b p s capacitors and termination resistors.

A standard cell library for implementing Rensselaer's Fast Reduced Instruction Set Computer (F-RISC/G) project with Rockwell's AlGaAs/GaAs Heterojunction Bipolar Transistor (HBT) technology is presented. The processor is targeted at an instruction cycle time of 1.0 ns. Difjerential Current Mode Logic (CML) is used, and unloaded gate delays are 15-20 P S .

This paper proposes a 3.4Gbps/lane intra-panel interface with 11.1% of the protocol overhead for the raw data to be transmitted. The proposed intra-panel interface uses a point-topoint interface architecture with embedded clock. To reduce the EMI radiation, the scrambling scheme was adopted. The protocol of the proposed intra-panel interface provides a PLL based clock and data recovery (CDR) scheme for the receiver. Timing controller (TCON) and source driver (SD) are implemented using 45nm/1.1V and 0.18um/1.8V CMOS processes, respectively. The proposed interface is verified on a 55-inch Full-HD TFT-LCD panel with 8bit RGB and 120-Hz frame rates. The maximum data rate per lane was measured as up to 3.4Gbps/lane.

-An intra-panel interface addressing all of the high-speed, low-power, and lowelectromagnetic interference (EMI) requirements for tablet personal computer applications is presented. This work proposes an adaptive clock window scheme to achieve 1.4-Gbps data-rate. For EMI suppression, data scrambling, horizontal blank period pattern scrambling, and novel clock and data recovery circuit are introduced. Lastly, for power-saving, the proposed interface dynamically biases source driver's output buffers and employs early charge sharing by controlling the configuration data. For verification, a WQXGA thin-film transistor liquid crystal display system is implemented with the timing controller and source driver ICs that are fabricated using 65-nm and 180-nm complementary metal-oxide semiconductor (CMOS) processes, respectively. The liquid crystal display system demonstrates maximum operation speed of 1.4 Gbps and suppression of EMI noise in LTE Band-20 and GSM 850 bands. The proposed power-saving schemes achieve 4.3% reduction in total power consumption by source driver IC, which reaches about 85% of power consumption by enhanced reduced-voltage differential signaling interface circuit.