A 51-dB SNDR DCO-based TDC using two-stage second-order noise shaping

Konishi, Tadataka; Okuno, Keisuke; Izumi, Shintaro; Yoshimoto, Masahiko; Kawaguchi, Hiroshi

doi:10.1109/iscas.2012.6271996

Cited by 5 publications

(4 citation statements)

References 7 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Since in many applications such as ADPLLs where TDCs function as a phase detector, we are only interested in the performance of TDCs over the loop bandwidth of the ADPLLs, system‐level approaches such as noise‐shaping obtained from ΔΣ operations can be utilised to reduce the quantisation noise of TDCs well below that of sampling TDCs over a specific frequency range [86]. These TDCs are termed noise‐shaping TDCs [6, 87–90]. Recent advance in TDCs utilises the intrinsic advantages of both resolution‐enhancing techniques such as interpolation in sampling TDCs and frequency‐dependent noise suppressing techniques such as ΔΣ operation of noise‐shaping TDCs simultaneously to improve the resolution of TDCs [91–93].…”

Section: Noise‐shaping Tdcsmentioning

confidence: 99%

“…The oscillator oscillates between two different oscillation states and becomes a switched ring oscillator (SRO), as shown in Fig. 16 [87, 90]. Since the charge of the capacitors at the output nodes of the oscillator at the end of ( k − 1)th phase is carried over in its entirety to the next k th phase, first‐order noise‐shaping characteristic intrinsic to GRO is preserved in SRO.…”

Section: Noise‐shaping Tdcsmentioning

confidence: 99%

See 1 more Smart Citation

CMOS time‐to‐digital converters for mixed‐mode signal processing

Yuan

2014

J. eng.

View full text Add to dashboard Cite

Section: Noise‐shaping Tdcsmentioning

confidence: 99%

Section: Noise‐shaping Tdcsmentioning

confidence: 99%

CMOS time‐to‐digital converters for mixed‐mode signal processing

Yuan

2014

J. eng.

View full text Add to dashboard Cite

“…In our proposed architecture, this frequency mismatch can be, however, compensated by a first-order LMS filter. The FSO presents advantages over a GRO by alleviating problems related to switching noise and transistor leakage [6]. In GRO's gating, the stored phase states are degraded or even lost.…”

Section: Proposed Frequency Shift Oscillator Tdc (Fsotdc)mentioning

confidence: 99%

A Second-Order All-Digital TDC with Low-Jitter Frequency Shift Oscillators and Dynamic Flipflops

Konishi

Okuno

Izumi

et al. 2013

IEICE Trans. Electron.

Self Cite

View full text Add to dashboard Cite

We present a small-area second-order all-digital time-todigital converter (TDC) with two frequency shift oscillators (FSOs) comprising inverter chains and dynamic flipflops featuring low jitter. The proposed FSOs can maintain their phase states through continuous oscillation, unlike conventional gated ring oscillators (GROs) that are affected by transistor leakage. Our proposed FSOTDC is more robust and is eligible for all-digital TDC architectures in recent leaky processes. Low-jitter dynamic flipflops are adopted as a quantization noise propagator (QNP). A frequency mismatch occurring between the two FSOs can be canceled out using a least mean squares (LMS) filter so that second-order noise shaping is possible. In a standard 65-nm CMOS process, an SNDR of 61 dB is achievable at an input bandwidth of 500 kHz and a sampling rate of 16 MHz, where the respective area and power are 700 μm 2 and 281 μW.

show abstract

“…All-digital noise-shaping TDCs can be implemented using either an open-loop or a closed-loop approach. Open-loop ΔΣ TDCs utilise the first-order noise-shaping of gated or switched ring oscillators [2][3][4][5][6][7][8][9][10]. The absence of a negative feedback mechanism makes these TDCs less resilience to the effect of PVT (process, voltage, temperature) uncertainty.…”

Section: Introductionmentioning

confidence: 99%

Time‐based all‐digital time‐to‐digital converter with pre‐skewed bi‐directional gated delay line time integrator

Yuan

Parekh

2019

IET Circuits, Devices & Systems

View full text Add to dashboard Cite

An all-digital first-order single-bit ΔΣ time-to-digital converter (TDC) with a pre-skewed bi-directional gated delay line (PS-BDGDL) time integrator with built-in self-quantisation is presented in this study. Pre-skewing is utilised to lower the perstage delay of the BDGDL and minimise the skew errors of BDGDLs. The impact of the strength and timing of pre-skewed is analysed. The reduction of skew errors obtained from pre-skewing is also analysed. A design methodology combating the impact of process uncertainty on the TDC is developed. The TDC is designed in an IBM 130 nm 1.2 V CMOS technology and analysed using Spectre from Cadence Design Systems with BSIM4 device models. Simulation results show that the impact of process spread on the performance of the TDC can be minimised by adjusting the delay of the key delay blocks and the perstage delay of the gated delay stages. The figure-of-merit of the TDC outperforms reported TDCs alike.

show abstract

A 51-dB SNDR DCO-based TDC using two-stage second-order noise shaping

Cited by 5 publications

References 7 publications

CMOS time‐to‐digital converters for mixed‐mode signal processing

CMOS time‐to‐digital converters for mixed‐mode signal processing

A Second-Order All-Digital TDC with Low-Jitter Frequency Shift Oscillators and Dynamic Flipflops

Time‐based all‐digital time‐to‐digital converter with pre‐skewed bi‐directional gated delay line time integrator

Contact Info

Product

Resources

About