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We present a small-area second-order all-digital time-to-digital converter (TDC) with two frequency shift oscillators (FSOs) comprising inverter chains and dynamic flipflops featuring low jitter. The proposed FSOs can maintain their phase states through continuous oscillation, unlike conventional gated ring oscillators (GROs) that are affected by transistor leakage. Our proposed FSOTDC is more robust and is eligible for all-digital TDC architectures in recent leaky processes. Low-jitter dynamic flipflops are adopted as a quantization noise propagator (QNP). A frequency mismatch occurring between the two FSOs can be canceled out using a least mean squares (LMS) filter so that second-order noise shaping is possible. In a standard 65-nm CMOS process, an SNDR of 61 dB is achievable at an input bandwidth of 500 kHz and a sampling rate of 16 MHz, where the respective area and power are 700 µm 2 and 281 μW.

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This report describes an all-digital phase-locked loop (ADPLL) with temperature-compensated settling time reduction. The novelty of this work is autonomous oscillation control word estimation without a look-up table or memory circuits. The proposed ADPLL includes a multi-phase oscillator as a digitally controlled oscillator (DCO). Digital timing error correction circuits are integrated to minimize the settling time that is degraded by phase conversion error. The ADPLL is fabricated using a 65 nm CMOS process. The test chip occupies 0.27 × 0.36 mm 2 . It achieves 2.23 ps RMS jitter and -224 dB FoM at 2.4 GHz output frequency with 8.85 mW power dissipation. Measurement results show that the 47% settling time is reduced by the proposed estimation block. The average settling time at 25 °C is 3 μs. I. 978-1-4799-4242-8/14/$31.00 c 2014 IEEE