A 61-dB SNDR 700 µm² second-order all-digital TDC with low-jitter frequency shift oscillators and dynamic flipflops

Abstract

We present a small-area second-order all-digital time-to-digital converter (TDC) with two frequency shift oscillators (FSOs) comprising inverter chains and dynamic flipflops featuring low jitter. The proposed FSOs can maintain their phase states through continuous oscillation, unlike conventional gated ring oscillators (GROs) that are affected by transistor leakage. Our proposed FSOTDC is more robust and is eligible for all-digital TDC architectures in recent leaky processes. Low-jitter dynamic flipflops are adopted as a quantization noise propagator (QNP). A frequency mismatch occurring between the two FSOs can be canceled out using a least mean squares (LMS) filter so that second-order noise shaping is possible. In a standard 65-nm CMOS process, an SNDR of 61 dB is achievable at an input bandwidth of 500 kHz and a sampling rate of 16 MHz, where the respective area and power are 700 µm 2 and 281 μW.

CMOS time‐to‐digital converters for mixed‐mode signal processing

“…Since in many applications such as ADPLLs where TDCs function as a phase detector, we are only interested in the performance of TDCs over the loop bandwidth of the ADPLLs, system‐level approaches such as noise‐shaping obtained from ΔΣ operations can be utilised to reduce the quantisation noise of TDCs well below that of sampling TDCs over a specific frequency range [86]. These TDCs are termed noise‐shaping TDCs [6, 87–90]. Recent advance in TDCs utilises the intrinsic advantages of both resolution‐enhancing techniques such as interpolation in sampling TDCs and frequency‐dependent noise suppressing techniques such as ΔΣ operation of noise‐shaping TDCs simultaneously to improve the resolution of TDCs [91–93].…”

Time‐based all‐digital time‐to‐digital converter with pre‐skewed bi‐directional gated delay line time integrator

“…All-digital noise-shaping TDCs can be implemented using either an open-loop or a closed-loop approach. Open-loop ΔΣ TDCs utilise the first-order noise-shaping of gated or switched ring oscillators [2][3][4][5][6][7][8][9][10]. The absence of a negative feedback mechanism makes these TDCs less resilience to the effect of PVT (process, voltage, temperature) uncertainty.…”

GRO‐TDC with gate‐switch‐based delay cell halving resolution limit

“…The Vernier delay line and time amplifier are commonly used as the structure for the fine conversion. Since the proposal of GRO-TDC, various noise-shaping TDCs such as a frequency shift oscillator TDC [11] and a multi-stage noiseshaping TDC [12] have been reported, and the noise-shaping TDC has been considered as one of the most efficient TDCs. However, the accurate normalization is difficult and complex.…”