A 55 nm triple gate oxide 9 metal layers SiGe BiCMOS technology featuring 320 GHz f&lt;inf&gt;T&lt;/inf&gt; / 370 GHz f&lt;inf&gt;MAX&lt;/inf&gt; HBT and high-Q millimeter-wave passives

Chevalier, P.; Avenier, G.; Ribes, G.; Montagne, A.; Canderle, E.; Céli, D.; Derrier, N.; Deglise, C.; Durand, C.; Quémerais, Thomas; Buczko, M.; Gloria, D.; Robin, O.; Petitdidier, S.; Campidelli, Y.; Abbate, F.; Gros-Jean, M.; Berthier, Ludovic; Chapon, J.D.; Leverd, F.; Jenny, C.; Richard, C.; Gourhant, Olivier; De-Buttet, C.; Beneyton, R.; Maury, P.; Joblot, S.; Favennec, L.; Guillermet, M.; Brun, P.; Courouble, Kristell; Haxaire, K.; Imbert, Guy; Gourvest, E.; Cossalter, J.; Saxod, O.; Tavernier, C.; Foussadier, Franck; Ramadout, B.; Bianchini, Ricardo; Julien, C.; Ney, D.; Rosa, J.; Haendler, S.; Carminati, Y.; Borot, B.

doi:10.1109/iedm.2014.7046978

Cited by 122 publications

(68 citation statements)

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“…For a three-stack CMOS inverter output stage, the optimum transistor width ratios for maximum drain efficiency were found to be W 2 /W 1 ≈ 0.7 and W 3 /W 1 ≈ 0.57 [18], with the minimum width p-MOSFET and n-MOSFET devices in the stack having to satisfy (3). In circuits where high drain efficiency is not the priority, marginal improvement in output power can be gained by sizing the devices larger than the minimum value set out by (3). This improvement in output power, at the expense of efficiency, occurs since larger devices can source the same current at a reduced V MIN voltage, but have the drawback of increasing the capacitive losses.…”

Section: A Large-swing Output Stagementioning

confidence: 95%

“…With cutoff (f T ) and maximum oscillation frequencies (f MAX ) of fully wired transistors now approaching or exceeding 400 GHz, InP HBT [2] and 55nm SiGe BiCMOS [3] technologies are the most likely candidates to satisfy the linearity and bandwidth specification of the analog electronics parts of these systems. At the same time, despite their lower speed and breakdown voltage, with careful layout design to curb the f MAX degradation of fully wired transistors, and with aggressively strained SiGe p-MOSFETs, nanoscale UTBB FD-SOI and FinFET CMOS technologies are uniquely positioned to enable highly integrated reconfigurable system solutions whose power consumption scales with the symbol rate and modulation format.…”

Section: Introductionmentioning

confidence: 99%

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A <inline-formula> <tex-math notation="LaTeX">$3\times 60\;\text{Gb/s}$</tex-math> </inline-formula> Transmitter/Repeater Front-End With <inline-formula> <tex-math notation="LaTeX">$4.3\;{\rm V}_{\rm PP}$</tex-math> </inline-formula> Single-Ended Output Swing in a 28nm UTBB FD-SOI Technology

Shopov

2016

IEEE J. Solid-State Circuits

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A versatile three-lane transmitter/repeater array was designed and manufactured in a production 28nm ultra-thin body and BOX (UTBB) FD-SOI CMOS technology. Each lane in the array can operate at 60 Gb/s with adjustable output swing between 2.6 and 4.3 VPP with a measured input sensitivity of 10 mVPP at 40 Gb/s, and requires at least 40mVPP input signal level to fully saturate the output driver for maximum swing operation at 60 Gb/s. Scaled, cascaded single-ended CMOS inverter transimpedance amplifiers with resistive and inductive feedback and interstage series inductive peaking were used to form the preamplifiers of each lane. These were optimized for maximum bandwidth and large gain, and drive the >4V PP swing seriesstacked cascoded CMOS inverter output stage. The single-ended CMOS-inverter topologies ensure that the total power consumption scales with the data rate and reduce the lane footprint to that of a ground-signal pad I/O. The measured lane-to-lane isolation is better than 40 dB up to 55 GHz, while the measured Tx-toRx dynamic range, defined as the ratio of the maximum output swing and corresponding minimum input voltage and sensitivity, is larger than 54 dB up to 40 Gb/s.

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Section: A Large-swing Output Stagementioning

confidence: 95%

Section: Introductionmentioning

confidence: 99%

A <inline-formula> <tex-math notation="LaTeX">$3\times 60\;\text{Gb/s}$</tex-math> </inline-formula> Transmitter/Repeater Front-End With <inline-formula> <tex-math notation="LaTeX">$4.3\;{\rm V}_{\rm PP}$</tex-math> </inline-formula> Single-Ended Output Swing in a 28nm UTBB FD-SOI Technology

Shopov

2016

IEEE J. Solid-State Circuits

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“…The vertical profile presented in Fig. 2 comes from the "approach 2" study presented in [10], where the recipes used in 55-nm BiCMOS (B55) [5] are tuned to account for the process thermal budget reduction in 28-nm FD-SOI. This profile is therefore not expected to be fully optimized for the best performance in C28FD.…”

Section: Fabrication Process and Vertical Profilesmentioning

confidence: 99%

“…The height of the SiGe HBT is limited by the pre-metal dielectric (PMD) thickness, which is less than 200 nm, while the emitter width is targeted to be smaller than 100 nm observed in B55 [5]. Optimizing all the dimensions of the transistor together with the doping profiles is therefore extremely important before starting the hardware based process developments.…”

Section: Conditions On the Electrical Performancementioning

confidence: 99%

“…The 570 GHZjMAX demonstrated in [4], shortening the gap with the 700 GHz target of DOTSEVEN, is primarily driven by the extrinsic base resistance (Rsx) reduction provided by the Elevated Extrinsic Base (EEB) and Epitaxial Base Link (EBL) architectures. In the RF2THZ SiSoC project, a conventional Double-Polysilicon Self-Aligned (DPSA) architecture using a SEG of the base featuring +320 GHz fr was successfully integrated into a 55-nm CMOS [5] benefIting from both a reduced process thermal budget and the advanced patterning capability of a 300-nm wafer line [6].…”

Section: Introductionmentioning

confidence: 99%

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Advanced Si/SiGe HBT architecture for 28-nm FD-SOI BiCMOS

Céli

Zimmer

et al. 2016

2016 IEEE Bipolar/BiCMOS Circuits and Technology Meeting (BCTM)

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This paper presents a novel Fully Self-Aligned (FSA) in [9]). In order to achieve this goal, the architecture is fIrstly Si/SiGe HBT architecture using Selective Epitaxial Growth evaluated and optimized by TCAD simulation before (SEG) and featuring an Epitaxial eXtrinsic Base Isolated from launching the fabrication process trials.the Collector (EXBIC). The one is integrated into the bulk area of the 28-nm FD-SOI CMOS technology developed atThe fIrst part of the paper presents the fabrication process STMicroelectronics. All the parameters of the architecture such flow and the key features of the EXBIC architecture. In the as the boron-doped base link, the emitter width and height, the second part, electrical performances of this architecture pedestal oxide and sidewall thicknesses are evaluated by TCAD integrated into the bulk area part (called "NO SO" for No SOl) simulation. A low base-collector capacitance, independent from of the C28FD are systematically evaluated by TCAD the extrinsic base doping is obtained. Optimized architecture simulations. All the technological parameters of the exhibits 420 GHZ/T and 780 GHZ/MAX. architecture such as the boron in-situ doped base link, the emitter width and height, the pedestal oxide and sidewall Keywords-BiCMOS, SiGe HBT, FD-SOl, TCAD, thicknesses are thoroughly investigated. The results are architecture, thermal budget, vertical profile.discussed in the last section, where we also draw the conclusion I.

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A 17 GHz inductorless low‐pass filter based on a quasi‐Sallen–Key approach

Bocciarelli

Centurelli

Monsurrò

et al. 2023

Circuit Theory & Apps

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SummaryIn this paper, an evolution of the Sallen–Key biquad architecture is presented, suitable for applications at very high frequency. The pole of the buffer amplifier is exploited as one of the poles of the biquad, therefore overcoming the constraints it poses on the maximum resonance frequency that can be achieved. This allows designing low‐pass filters with cutoff frequencies above 10 GHz without using bulky inductors and with good linearity performance provided by the use of feedback. This approach has been exploited to design a biquad in a commercial SiGe BiCMOS technology with maximum of about 320 GHz. The biquad has been designed to provide a resonance frequency of 12 GHz and a quality factor Q of 1.9; postlayout simulations show a cutoff frequency in excess of 17 GHz, 15.75 mW of power consumption, an equivalent input noise below 1 Vrms, and −52 dB of total harmonic distortion (THD) for a 640 mVpp input signal, with a very limited area consumption.

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A 55 nm triple gate oxide 9 metal layers SiGe BiCMOS technology featuring 320 GHz f<inf>T</inf> / 370 GHz f<inf>MAX</inf> HBT and high-Q millimeter-wave passives

Cited by 122 publications

References 1 publication

A <inline-formula> <tex-math notation="LaTeX">$3\times 60\;\text{Gb/s}$</tex-math> </inline-formula> Transmitter/Repeater Front-End With <inline-formula> <tex-math notation="LaTeX">$4.3\;{\rm V}_{\rm PP}$</tex-math> </inline-formula> Single-Ended Output Swing in a 28nm UTBB FD-SOI Technology

A <inline-formula> <tex-math notation="LaTeX">$3\times 60\;\text{Gb/s}$</tex-math> </inline-formula> Transmitter/Repeater Front-End With <inline-formula> <tex-math notation="LaTeX">$4.3\;{\rm V}_{\rm PP}$</tex-math> </inline-formula> Single-Ended Output Swing in a 28nm UTBB FD-SOI Technology

Advanced Si/SiGe HBT architecture for 28-nm FD-SOI BiCMOS

A 17 GHz inductorless low‐pass filter based on a quasi‐Sallen–Key approach

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