A 56-mW 23-&amp;lt;tex&amp;gt;$hbox mm^2$&amp;lt;/tex&amp;gt;Single-Chip 180-nm CMOS GPS Receiver With 27.2-mW 4.1-&amp;lt;tex&amp;gt;$hbox mm^2$&amp;lt;/tex&amp;gt;Radio

Gramegna, G.; Mattos, P.G.; Losi, M.; Das, Shidhartha; Franciotta, M.; Bellantone, N.G.; Vaiana, Michele; Mandara, V.; Paparo, M.

doi:10.1109/jssc.2005.864136

Cited by 49 publications

(6 citation statements)

References 9 publications

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“…Although the power of the synthesizers in Refs. [12][13][14] is smaller than that in this work, the phase noise and spur are less attractive. Additionally, the synthesizers in Refs.…”

Section: Resultsmentioning

confidence: 73%

A low-power CMOS frequency synthesizer for GPS receivers

Jian-lian²,

Shimao

et al. 2010

J. Semicond.

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A low-power frequency synthesizer for GPS/Galileo L1/E1 band receivers implemented in a 0.18 m CMOS process is introduced. By adding clock-controlled transistors at latch outputs to reduce the time constant at sensing time, the working frequency of the high-speed source-coupled logic prescaler supplying quadrature local oscillator signals has been increased, compared with traditional prescalers. Measurement results show that this synthesizer achieves an in-band phase noise of -87 dBc/Hz at 15 kHz offset, with spurs less than -65 dBc. The whole synthesizer consumes 6 mA in the case of a 1.8 V supply, and its core area is 0.6 mm 2 .

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“…Although the power of the synthesizers in Refs. [12][13][14] is smaller than that in this work, the phase noise and spur are less attractive. Additionally, the synthesizers in Refs.…”

Section: Resultsmentioning

confidence: 73%

A low-power CMOS frequency synthesizer for GPS receivers

Jian-lian²,

Shimao

et al. 2010

J. Semicond.

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“…Applications relying on GNSS positioning have become a part of everyday life, leading to an increased variety of Location-Based Services (LBS). Nowadays, the LBS consumer market is dominated by single frequency (typically L1/E1 band), low cost and highly integrated GNSS receivers [3][4][5][6][7][8][9]. The use of such receivers comes with two main limitations: low precision and low reliability.…”

Section: Introductionmentioning

confidence: 99%

NaviSoC: High-Accuracy Low-Power GNSS SoC with an Integrated Application Processor

Borejko

Marcinek

Siwiec

et al. 2020

Sensors

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A dual-frequency all-in-one Global Navigation Satellite System (GNSS) receiver with a multi-core 32-bit RISC (reduced instruction set computing) application processor was integrated and manufactured as a System-on-Chip (SoC) in a 110 nm CMOS (complementary metal-oxide semiconductor) process. The GNSS RF (radio frequency) front-end with baseband navigation engine is able to receive, simultaneously, Galileo (European Global Satellite Navigation System) E1/E5ab, GPS (US Global Positioning System) L1/L1C/L5, BeiDou (Chinese Navigation Satellite System) B1/B2, GLONASS (GLObal NAvigation Satellite System of Russian Government) L1/L3/L5, QZSS (Quasi-Zenith Satellite System development by the Japanese government) L1/L5 and IRNSS (Indian Regional Navigation Satellite System) L5, as well as all SBAS (Satellite Based Augmentation System) signals. The ability of the GNSS to detect such a broad range of signals allows for high-accuracy positioning. The whole SoC (system-on-chip), which is connected to a small passive antenna, provides precise position, velocity and time or raw GNSS data for hybridization with the IMU (inertial measurement unit) without the need for an external application processor. Additionally, user application can be executed directly in the SoC. It works in the −40 to +105 °C temperature range with a 1.5 V supply. The assembled test-chip takes 100 pins in a QFN (quad-flat no-leads) package and needs only a quartz crystal for the on-chip reference clock driver and optional SAW (surface acoustic wave) filters. The radio performance for both wideband (52 MHz) channels centered at L1/E1 and L5/E5 is NF = 2.3 dB, G = 131 dB, with 121 dBc/Hz of phase noise @ 1 MHz offset from the carrier, consumes 35 mW and occupies a 4.5 mm2 silicon area. The SoC reported in the paper is the first ever dual-frequency single-chip GNSS receiver equipped with a multi-core application microcontroller integrated with embedded flash memory for the user application program.

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“…Active resistor-capacitor (RC) filters are also quite common in GNSS chipsets. These offer the benefit that they can be implemented internally to the chip, see, eg, Gramegna et al 22…”

Section: Lumped Component Filtersmentioning

confidence: 99%

An overview of the effects of out‐of‐band interference on GNSS receivers

Hegarty

Bobyn²,

Grabowski

et al. 2020

NAVIGATION

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This paper addresses the wide range of mechanisms through which out‐of‐band interference can disrupt the functioning of GNSS receivers. These mechanisms include saturation and desensitization of front‐end low noise amplifiers, mixers and other circuitry; reciprocal mixing effects that arise from the fact that receivers cannot generate a perfect tone to down‐convert the desired signals; intermodulation products; aliasing of out‐of‐band emissions that remain after filtering into the receiver's passband; and the reception of in‐band (to GNSS) emissions that are always present due to imperfections in the signal generation and filtering of the interfering system. These mechanisms are described in detail and mitigation approaches for each are discussed.

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A 56-mW 23-<tex>$hbox mm^2$</tex>Single-Chip 180-nm CMOS GPS Receiver With 27.2-mW 4.1-<tex>$hbox mm^2$</tex>Radio

Cited by 49 publications

References 9 publications

A low-power CMOS frequency synthesizer for GPS receivers

A low-power CMOS frequency synthesizer for GPS receivers

NaviSoC: High-Accuracy Low-Power GNSS SoC with an Integrated Application Processor

An overview of the effects of out‐of‐band interference on GNSS receivers

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