A 5GHz 7nm L1 cache memory compiler for high-speed computing and mobile applications

Unveiling Enhanced Trade-offs in SRAM-based Memory Arrays for Cryogenic CMOS Technology

“…Cryogenic SRAM are also utilized HP computing systems. Apart from the high-performance core, HP computing systems primarily consist of buffers and SRAM-based caches [8], [9], [25]. These caches are designed at multiple levels to fulfill the timing and area constraints of the HP computing systems.…”

“…The performance of the SRAM can be improved by operating at a higher V DD at the cost of higher power consumption. Since power is one of the major constraints in QCs, high-performance computing, and space electronics, we have performed the entire analysis for SRAM operating at a frequency of 2 GHz and nominal V DD instead of increasing the V DD for speed enhancement, as has been done in [25]. The operating frequency of 2 GHz is chosen to satisfy the timing constraints of a few ns imposed by QCs.…”

“…Several assist techniques based on the assist knobs (e.g., WL, BL, V DD , etc.) have been reported in the literature to improve the SRAM performance and array size [25], [34], [35]. Based on the SRAM operations, these assist techniques can also be categorized as read assist and write assist schemes.…”

“…However, one of the primary limitation factors of state-of-the-art computing systems is efficient on-chip data transfer. The speed of the overall system in high-performance computing is mainly restricted by the L1 cache performance and static power consumption [25]. The leakage current and, hence, static power consumption in CMOS transistors decreases by many orders at cryogenic temperatures.…”

An Open-Source RRAM Compiler

“…However, customised memory design is a difficult and time consuming task [5]- [7]. As a result, a number of memory compilers has been presented before [5]- [10].…”