A 6.4Gb/s CMOS SerDes core with feedforward and decision-feedback equalization

2 Gbps SerDes design based on IBM Cu-11 (130nm) standard cell technology

“…The reasons that SerDes has not enjoyed widespread adoption are (1) design time inefficiency, (2) high power requirements, (3) channel bit error rate (BER) and (4) silicon area cost. The recent surge in low voltage differential signaling (LVDS) technology and its common-mode versatility has partially solved the problem of channel bandwidth and BER problem [11], but still all known state-of-the-art SerDes designs like IBM High Speed SerDes (HSS) [10] are complex, area-intensive and power hungry which make them not suitable for medium and low-budget projects.…”

“…A clock multiplier is one of the very important components of SerDes system. In conventional high-speed SerDes systems like [8], [10], 0 and [5], to achieve maximum bandwidth and pack large number of parallel data lines to one serial link, low-jitter fast-locking PLL based clock multipliers/frequency synthesizers are used to drive the parallel to serial converters. Similarly a clock recovery circuit, on the receiver side, employs sophisticated PLLs or DLLs to recover the clock on the receiver end to capture and deserialize data back to a parallel form.…”

Recent advances in high-speed serial I/O trends, standards and techniques

“…around 12Gb/s). Using an FFE and DFE together addresses these concerns [10,11,[15][16][17]. In [10], a backplane link transceiver architecture, implemented in 0.13µm CMOS technology, incorporates a 4-tap FFE (FIR) that in conjunction with a DFE enables 6.25/12.5Gb/s data transmission.…”

On-chip data communication : analysis, optimization and circuit design

“…This is especially so when loop-unrolling (see section 7.6) is used, because then there is no single stable transition point for a phase-detector to use, as discussed in [116,138]. So for many receivers with loop-unrolled DFE, the CDR is a standalone circuit that primarily uses the input signal to the DFE for phase detection [100,111,114], possibly also taking some information from the DFE output into account [135,141].…”

“…The wanted value at the sample-instant is often called the 'cursor' sample when it is discussed in relation to the unwanted pre-cursor or post-cursor ISI samples [99,100]. Postcursor ISI is the most common (at least for on-chip communication) and is caused by nonzero levels of the symbol response at multiples of the symbol-time (t=t d + k·T s , k=1,2,3…) after the cursor.…”