A 6.75–8.25-GHz −250-dB FoM Rapid ON/OFF Fractional-N Injection-Locked Clock Multiplier

A Charge-Sharing Locking Technique With a General Phase Noise Theory of Injection Locking

“…For a practical CSL frequency synthesizer, PN of the reference must be considered. In this case, taking N = 50 (i.e., f ref = 200 MHz) and L ref = 10 −160/10 rad 2 /Hz [i.e., rms jitter σ t,ref = 112.5 fs; see (19)] into consideration, the simulated PN and analytical results from (22) for different β are shown in Fig. 7(d), both of which match nearly perfectly.…”

“…Fig. 16(a)-(d) shows the measured rms jitter (integrated from 10 kHz to 30 MHz 18 ) at 76-77 fs and reference spurs 19 at −45∼−43 dBc from 26.25 to 21.75 GHz. To account for the third-harmonic extraction, the reference spur for the fundamental frequency of 8.75-7.25 GHz is around −53 dBc after subtracting 20 log 10 (3) = 9.54 dB.…”

“…The early high-speed time-to-digital converter (TDC)-based [14] or VCO-replica-based FTLs [15] consume huge power and area. A gated-pulse technique was applied in [16] and [19] in which some reference cycles are exclusively devoted for IL, while others stop the IL altogether and exclusively use the FTL. Unfortunately, this requires a relatively complex timing control based on several digitally controlled delay lines (DCDLs).…”

“…Surprisingly, a general PN theory in IL is still missing [24]- [26]. The conventional s-or z-domain (at reference rate) analyzing techniques [16], [19], [26], [27] model ILOs in the same manner as in the conventional type-I PLLs with a single integrating pole [28], but they fail to predict the ILO's special PN phenomena, such as the extremely strong suppressing ability of the oscillator's PN and the PN folding effect resulting in the ILO's PN being 3 dB higher outside of the "loop" bandwidth than when the oscillator is free-running [22], [23], [29]- [31]. Combining a discrete-time model with a continuous-time zero-order hold (ZOH) function, Ye et al [13] derived a pioneering but provisional PN model of an ILO.…”

A 5.4-GHz 2/3/4-Modulus Fractional Frequency Divider Circuit in 28-nm CMOS

“…Typically, a single highly precise frequency reference, such as a crystal oscillator, is applied, and indirect frequency synthesis via fractional-N phase-locked loops is ubiquitously used for highfrequency signal generation. Recently, there has been research activity to further improve the frequency range, resolution, and settling time of such frequency generation by using fractional frequency dividers [1]- [6] and multipliers [7]- [10].…”