A 6-bit 2.5-GS/s flash ADC using comparator redundancy for low power in 90 nm CMOS

Sundström, Timmy; Alvandpour, Atila

doi:10.1007/s10470-009-9391-x

Cited by 9 publications

(1 citation statement)

References 15 publications

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“…At this relatively low resolution, the straight forward full-flash architecture seems best suited for the high speed data converter. However, flash ADCs in CMOS technology suffer greatly from random offsets in the comparators which can easily exceed the least significant bit (LSB) [2], defined as 3rV os;comp…”

Section: Introductionmentioning

confidence: 99%

A termination scheme using intended asymmetric spatial filter response for averaging flash A/D converter

Wang

Dehollain

Hong

2012

Analog Integr Circ Sig Process

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Averaging network is adopted to reduce the front-end amplifier's offset in the flash analog-to-digital converter (ADC) commonly at the cost of the boundary threshold error. Such error worsens the integral-nonlinearity and introduces distortion. An averaging termination scheme using intended asymmetric spatial filter response is proposed to overcome this problem. It matches the impulse response window width, W IR , to the active zero-crossing response window width, W ZX at the boundary of network. Analysis and simulation show that by tuning the ratio between termination resistor R T and averaging resistor R 1 , the boundary error is reduced as close as to 1%. This method provides sufficient reliability since the resistance matching can be fabricated as high as 1% in modern CMOS technology. Its feasibility for the flash ADC has been validated by a 1GS/s 4-bit flash converter.

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Section: Introductionmentioning

confidence: 99%

A termination scheme using intended asymmetric spatial filter response for averaging flash A/D converter

Wang

Dehollain

Hong

2012

Analog Integr Circ Sig Process

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4- and 6-GS/s 4-bit frequency-translating hybrid ADCs in 90-nm CMOS

Mazlouman

Sheikhaei

Mirabbasi

2011

Analog Integr Circ Sig Process

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Two frequency-translating hybrid analog-todigital converters (FTH-ADCs) are implemented using building blocks that are designed and fabricated in a 90-nm CMOS technology. These blocks include a mixer, a filter, and an ADC that are cascaded to build each analog processing path of the FTH-ADC. The mixer-filter path is designed with sufficient linearity and signal-to-noise-anddistortion ratio (SNDR) to accommodate for the desired resolution of the path ADC. A 4-bit flash ADC structure is used in each path. This path has a signal bandwidth of 0.5 GHz and frequency-translates the input signal into baseband and digitizes it with the sample rate of 2 GHz. Multiple such mixer-filter-ADC paths are then combined together with proper mixing frequencies in order to implement two-and three-channel ADC systems. The twoand three-channel systems have overall input bandwidths of 2 and 3 GHz and effective conversion rates of 4 and 6 GS/s, respectively, while maintaining their single-path resolution across their entire input bandwidths. The implemented architecture provides an extendible solution to improve the speed of ADCs by incorporating them in an FTH-ADC architecture.

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Design of a parallel low power flash A/D converter for the sub-sampling IR-UWB receiver

Wang

Dehollain

Hong

2012

Analog Integr Circ Sig Process

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A 6-bit 2.5-GS/s flash ADC using comparator redundancy for low power in 90 nm CMOS

Cited by 9 publications

References 15 publications

A termination scheme using intended asymmetric spatial filter response for averaging flash A/D converter

A termination scheme using intended asymmetric spatial filter response for averaging flash A/D converter

4- and 6-GS/s 4-bit frequency-translating hybrid ADCs in 90-nm CMOS

Design of a parallel low power flash A/D converter for the sub-sampling IR-UWB receiver

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