A 60-GHz OOK Receiver With an On-Chip Antenna in 90 nm CMOS

This paper presents a fully integrated 40-GHz transceiver designed for 2 Gbit/s short-range chip-to-chip communication link. The proposed architecture includes both the transmitter and the receiver and is optimized for on-off-keying modulation scheme. The transceiver design includes two variants, which can drive either a planar onchip antenna or wire-bonded off-chip antenna. The performance comparison of these is given in the paper. A compact and energy-efficient technique has been adopted by directly modulating the oscillator in the transmitter. The receiver uses a self-mixing topology followed by transimpedance amplifier and a limiter chain. The detailed circuit descriptions as well as design trade-offs with simulation results in 65 nm CMOS are given. In addition, an example design modification to extend the modulation to 4-level amplitude shift keying is presented.

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“…(1)(2)(3)(4)(5), plots of minimum required input and corresponding maximum operation distance as a function of LNA gain are shown in Fig. 3.…”

Section: System Sensitivitymentioning

confidence: 99%

“…Easiest solution for implementation is to use planar dipole antenna or its variant [13]. There are several different approaches to improve performance, but these require additional processing steps in manufacturing and thus increase complexity and costs [4,14]. Another tempting topology is to use wire bond antennas [15][16][17].…”

Section: Antenna Structuresmentioning

confidence: 99%

A 40 GHz wireless link for chip-to-chip communication in 65 nm CMOS

Tikka

Viitala

Ryynänen

2015

Analog Integr Circ Sig Process

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“…A very well-known LNA figure of merit [16], here reported in (1), is calculated for all the considered amplifiers and shown in Table 1. It has to be noticed that in this calculation a factor n is added for a fairer comparison, taking into account that differential topologies have double-power consumption.…”

Section: V M E a S U R E M E N T S V E R S U S S I M U L A T I O N Smentioning

confidence: 99%

A 60 GHz fully differential LNA in 90 nm CMOS technology

Malignaggi

Hamidian

Boeck

2013

Int. j. microw. wirel. technol.

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The present paper presents a fully differential 60 GHz four stages low-noise amplifier for wireless applications. The amplifier has been optimized for low-noise, high-gain, and low-power consumption, and implemented in a 90 nm low-power CMOS technology. Matching and common-mode rejection networks have been realized using shielded coplanar transmission lines. The amplifier achieves a peak small-signal gain of 21.3 dB and an average noise figure of 5.4 dB along with power consumption of 30 mW and occupying only 0.38 mm 2 pads included. The detailed design procedure and the achieved measurement results are presented in this work.

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“…With the need for high communication speed in the upcoming 5G communication system, the millimeter-wave (mm-wave) bands are attractive because of the large absolute bandwidth [1,2]. PA is one of the key components that restrict the performance of mm-wave band transceivers.…”

Section: Introductionmentioning

confidence: 99%

A wideband high efficiency V-band 65 nm CMOS power amplifier with neutralization and harmonic controlling

Chen

Jiang

Zhao

et al. 2017

IEICE Electron. Express

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A wideband high-efficiency V-band CMOS power amplifier (PA) is proposed in this paper. Neutralization technique is used to reduce the Miller effect and improve the power gain. A wideband on-chip transformer is used to adjust the transistors' voltage waveform to improve the PAE performance. The PA works from 51 GHz to 64 GHz with 13 GHz absolute bandwidth and 22.6% relative bandwidth. The output power reaches 14.9 dBm with 16.3% peak PAE. The circuit is designed in a 65 nm CMOS technology.

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A 60-GHz OOK Receiver With an On-Chip Antenna in 90 nm CMOS

Cited by 122 publications

References 29 publications

A 40 GHz wireless link for chip-to-chip communication in 65 nm CMOS

A 40 GHz wireless link for chip-to-chip communication in 65 nm CMOS

A 60 GHz fully differential LNA in 90 nm CMOS technology

A wideband high efficiency V-band 65 nm CMOS power amplifier with neutralization and harmonic controlling

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