A 62.5 Gb/s multi-standard SerDes IC

Partovi, H.; Evans, Brian; Wilson, Tegan; Shelton, Stefon; Naviasky, E.; Sanjeevi, E.; Yi, Wen; Gopalakrishnan, Karthik; Chokkalingam, S.; Thompson, H. W.; Casas, M. P.; Ye, Lingting; Hufford, M.; Qiu, Yujing; Williams, Matthew; James, J.B.; Baldiserotto, A.; White, Sean; Williams, S.; Georgantas, D.; Gray, T. A.

doi:10.1109/cicc.2003.1249466

Cited by 6 publications

(1 citation statement)

References 2 publications

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“…While phase-locked loop (PLL) based CDRs can operate at very high speeds and can lock exactly on the frequency of the received data. Their high power consumption, tight jitter performance, and large silicon area consumed by loop filter, make them less attractive for multi-channel applications [1]- [3]. On the other hand, dual-loop delay-locked loop (DLL) based or phase-interpolation (PI) based CDRs are widely used in multi-channel receivers [4].…”

Section: Introductionmentioning

confidence: 99%

A low-power, multichannel gated oscillator-based CDR for short-haul applications

Tajalli

Müller

Atarodi

et al. 2005

Proceedings of the 2005 International Symposium on Low Power Electronics and Design - ISLPED '05

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A gated current-controlled oscillator (GCCO) based topology is used to implement a low-power multi-channel clock and data recovery (CDR) system in a 0.18um digital CMOS technology. A systematic approach is presented to design a reliable and lowpower system based on the required specifications. Behavioral simulations are also used to estimate the achievable bit error rate (BER), jitter tolerance (JTOL), and frequency offset tolerance (FTOL) of the proposed CDR. Using a single 1.8V supply voltage, the proposed 20Gbps 8-channel CDR consumes only 70.2mW or 3.51mW/Channel/Gbps while occupies 0.045mm 2 silicon area.

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Section: Introductionmentioning

confidence: 99%

A low-power, multichannel gated oscillator-based CDR for short-haul applications

Tajalli

Müller

Atarodi

et al. 2005

Proceedings of the 2005 International Symposium on Low Power Electronics and Design - ISLPED '05

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An ASIC-Ready 1.25–6.25Gb/s SerDes in 90nm CMOS with multi-standard compatibility

Nishi

Abe

Ribo

et al. 2008

2008 IEEE Asian Solid-State Circuits Conference

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Recent developments in high-performance system-on-chip IC design

Khan¹

2004 International Conference on Integrated Circuit Design and Technology (IEEE Cat. No.04EX866)

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A 62.5 Gb/s multi-standard SerDes IC

Cited by 6 publications

References 2 publications

A low-power, multichannel gated oscillator-based CDR for short-haul applications

A low-power, multichannel gated oscillator-based CDR for short-haul applications

An ASIC-Ready 1.25–6.25Gb/s SerDes in 90nm CMOS with multi-standard compatibility

Recent developments in high-performance system-on-chip IC design

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A 62.5 Gb/s multi-standard SerDes IC

Cited by 6 publications

References 2 publications

A low-power, multichannel gated oscillator-based CDR for short-haul applications

A low-power, multichannel gated oscillator-based CDR for short-haul applications

An ASIC-Ready 1.25&#x2013;6.25Gb/s SerDes in 90nm CMOS with multi-standard compatibility

Recent developments in high-performance system-on-chip IC design

Contact Info

Product

Resources

About

An ASIC-Ready 1.25–6.25Gb/s SerDes in 90nm CMOS with multi-standard compatibility