A 667-Mb/s Operating Digital DLL Architecture for 512-Mb DDR SDRAM

Hamamoto, T.; Furutani, K.; Kubo, Tetsuo; Kawasaki, S.; Iga, H.; Kimura, Takashi; Konishi, Y.; Yoshihara, T.

doi:10.1109/jssc.2003.820851

Cited by 32 publications

(7 citation statements)

References 11 publications

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“…Referring to an input clock frequency of 1 GHz, valid locking values (T/ock) for the cell delay are indicated (dashed lines), as well as the relevant number Np of periods to which the delay-line is locked. It is important to note that the locking is always guaranteed, provided that the cell delay range in all t~e conditions is larger than the distance between 2 valId values of the cell delay, which is equal to the time-bin size expressed by (2). Therefore, a cell delay range of only 16.39 ps is sufficient to lock the delay line in~ll the operating conditions, with the above mentIoned parameters of 61 cells and 1 GHz clock frequency.…”

Section: Simulation Resultsmentioning

confidence: 99%

“…With this method, the num?er of locking periods is variable and the false-lockIng problem no longer exists. Moreover, being Np itself a variable, the locking condition expressed by (2) can be satisfied with a smaller range of Te. In fact, the line can be locked to a different number of periods in different environmental or process conditions, so that the cell-delay range necessary to guarantee the locking, is greatly reduced as compared with all the o~her realizations.…”

Section: Multiple-period Dllmentioning

confidence: 99%

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Self-adjusting multiple-period locked delay line For high-resolution multiphase clock generation

Baronti¹,

Lunardini²,

Roncella³

et al. 2005

2005 12th IEEE International Conference on Electronics, Circuits and Systems

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We present a novel Delay-Locked Loop (DLL) based architecture for multiphase clock generation with a time resolution finer than the gate delay. The basic idea consists in locking the delay line to a certain multiple of clock periods that is not fixed a priori, but is self-adjusted depending on process and operating conditions, and working frequency. In such a way, a wide locking range is achieved with a very compact delay cell structure. The circuit has been used to design a new TDC architecture in which a resolution (time-bin size) of about 16 ps is reached using a 0.35 J..lm CMOS technology. Post-layout simulations show the feasibility of the technique.

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Section: Simulation Resultsmentioning

confidence: 99%

Section: Multiple-period Dllmentioning

confidence: 99%

Self-adjusting multiple-period locked delay line For high-resolution multiphase clock generation

Baronti¹,

Lunardini²,

Roncella³

et al. 2005

2005 12th IEEE International Conference on Electronics, Circuits and Systems

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show abstract

“…The total delay through , , , the edge combiner, the buffer, and can be calculated as (2) Compared with (1) and (2), the total delay between and is equal to . In general, let us compare the phases between and ( , , and ).…”

Section: Circuit Descriptionmentioning

confidence: 99%

“…T HE delay-locked loop (DLL) is widely used for clock generation [1], clock deskewing [2], and data recovery [3]. In the recent years, the speed demand for the data transmission rate between chips is increasing.…”

Section: Introductionmentioning

confidence: 99%

A 3–8 GHz Delay-Locked Loop With Cycle Jitter Calibration

Chuang

Liu

2008

IEEE Trans. Circuits Syst. II

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A 3-8 GHz delay-locked loop (DLL) with cycle jitter calibration is presented. To lower the operation frequency of a voltage-controlled delay line (VCDL), this DLL adopts the dividers, an edge combiner, and the multiple VCDLs. A duty cycle correction circuit is presented to maintain the output duty cycle of 50%. This DLL has been fabricated in 90-nm CMOS process. The measured peak-to-peak jitters at 8 GHz are 11.44 and 6.67 ps before and after calibration, respectively. The power dissipation at 8 GHz is 18 mW for a supply voltage of 1.2 V, and the measured output duty cycle variation is less than 3%.

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“…A stable low-jitter clock generator is required to transfer data correctly at multi-gigabit rates for a highperformance memory interface. A multi-phase digital delay-locked loop (DLL) is used in the memory interface owing to its simplicity and short wake-up time from sleep-mode [1][2][3][4][5][6]. However, the output jitter of the digital DLL is limited to the time resolution of the delay cells.…”

mentioning

confidence: 99%

Low-jitter multi-phase digital DLL with closest edge selection scheme for DDR memory interface

Kim

Park

et al. 2008

Electron. Lett.

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A multi-phase digital delay-locked loop (DLL) capable of a low-jitter feature for DDR memory interface is reported. The DLL repeatedly selects the output clock edge which is closest to the reference clock edge to reduce the total jitter. A test chip was fabricated in a 0.18 mm CMOS process to verify its functionality. The measured RMS and peak-to-peak jitter of the DLL are 6.2 and 20.4 ps, respectively. The power consumption of the DLL is 12 mW from a 1.8 V supply voltage.

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A 667-Mb/s Operating Digital DLL Architecture for 512-Mb DDR SDRAM

Cited by 32 publications

References 11 publications

Self-adjusting multiple-period locked delay line For high-resolution multiphase clock generation

Self-adjusting multiple-period locked delay line For high-resolution multiphase clock generation

A 3–8 GHz Delay-Locked Loop With Cycle Jitter Calibration

Low-jitter multi-phase digital DLL with closest edge selection scheme for DDR memory interface

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