A 6bit, 1.2GSps low-power flash-ADC in 0.13μm digital CMOS

Abstract

A 6bit flash-ADC with 1.2GSps, wide analog bandwidth and low power, realized in a standard digital 0.13µm CMOS copper technology is presented. Employing capacitive interpolation gives various advantages when designing for low power: no need for a reference resistor ladder, implicit sample-and-hold operation, no edge effects in the interpolation network (as compared to resistive interpolation), and a very low input capacitance of only 400fF, which leads to an easily drivable analog converter interface.Operating at 1.2GSps the ADC achieves an effective resolution bandwidth (ERBW) of 700MHz, while consuming 160mW of power. At 600MSps we achieve an ERBW of 600MHz with only 90mW power consumption, both from a 1.5V supply. This corresponds to outstanding Figure-of-Merit numbers (FoM) of 2.2 and 1.5pJ/convstep, respectively. The module area is 0.12mm².

A 52mW 10b 210MS/s two-step ADC for digital-IF receivers in 0.13μm CMOS

“…Stage-1 preamplifier decreases/increases its load resistance in reset/amplification phase to speed up settling/increase gain. While stage 1 uses output offset storage, stage 2~3 uses input/output offset storage [4], which is more power efficient than output offset storage. During reset, when the interpolation capacitors are charged, the impedance is low (1/gm of the input device) to satisfy settling speed requirement.…”

ADC precision requirement for digital ultra-wideband receivers with sublinear front-ends: a power and performance perspective

“…Efficient implementations of such high speed ADCs mandate the use of flash architectures which exhibit an exponential increase in comparator area and power with the resolution specification. State of the art flash ADCs reported in [6], [7], and [8] have a maximum resolution of six bits while consuming significant power and occupying substantial chip area. Steep tradeoffs between the ADC's performance and implementation costs have prompted authors in [4,5] to investigate the minimum precision necessary to maintain accurate data detection.…”

A 31.2mW UWB Baseband Transceiver with All-Digital I/Q-Mismatch Calibration and Dynamic Sampling

“…Measured results show that the proposed design achieves maximum 480Mb/s data rate with 31.2mW power consumption. The power overhead is only 13.18mW with IQM calibration, DSTC, and PTCG, resulting in 5.4dB SNR improvement for typical 8% PER and 43.75% ADC power saving [2]. …”

“…By the proposed DSTC and phase-tunable clock generator (PTCG), the sampling frequency is reduced to Baud rate, i.e. 1x signal bandwidth, resulting in 70mW×2 ADC power saving [2]. So, signals are sampled at their optimum timing, and system PER is improved by 2.3dB SNR.…”

“…In ultra wideband (UWB) system, I/Q mismatch (IQM) from RF circuits degrades system packet error rate (PER) performance, and ADC circuit consumes about 50% analog front-end power (ADC×2+RF) [1] [2]. For high IQM tolerance and ADC power saving, a Multi-Band OFDM (MB-OFDM) UWB baseband transceiver with digital IQM calibration and dynamic sampling timing controller (DSTC) is proposed here, comprising high performance and low power dissipation of wireless UWB applications.…”