A 71dB-SNDR 50MS/s 4.2mW CMOS SAR ADC by SNR enhancement techniques utilizing noise

Matsukawa, Takashi; Miki, Takuji; Matsukawa, Kazuo; Bando, Yoji; Okumoto, Takeshi; Okihara, Koji; Sakiyama, Shiro; Dosho, Shiro

doi:10.1109/isscc.2013.6487731

Cited by 48 publications

(24 citation statements)

References 2 publications

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“…Normally SAR ADCs show very high energy efficiency, but due to comparator noise and capacitor mismatch, SAR ADCs are limited to medium resolution. To overcome the effect of capacitor mismatch, binary weighted capacitance array in DACs has been implemented in [1], [2]. An alternative technique called dithering has been proposed to cancel the errors in the DAC and also to improve the linearity [3], [4].…”

Section: Introductionmentioning

confidence: 99%

A 14-bit 10kS/s power efficient 65nm SAR ADC for cardiac implantable medical devices

Dastagiri¹,

Kishore²

2018

IJET

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This brief presents a 10kS/s 14 bit 12.5 ENOB Successive Approximation Register Analog-to-Digital Converter for Cardiac Implantable Medical. For achieving power efficient operation, SAR ADC employ SAR control, a new power and noise efficient comparator topology, non-binary weighted capacitive DAC. The linearity of implemented SAR ADC is enhanced with the uniform geometry of non-binary weighted capacitive DAC.The proposed SAR ADC is implemented using 65nm CMOS technology. The latched comparator consumes a power of 2.4uW and it provides an ENOB of 12.6 at a supply voltage of 1V.The INL is between -2.7/+1.6 LSB and DNL is between -0.6/+1.4LSB. The FOM of ADC is 40fJ/conv.Step which is comparable with existing ADC topologies.

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Section: Introductionmentioning

confidence: 99%

A 14-bit 10kS/s power efficient 65nm SAR ADC for cardiac implantable medical devices

Dastagiri¹,

Kishore²

2018

IJET

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“…In [69] and [70], dithering technique has been applied to effecitvely suppress the spurs and improve the DAC linearity. The added dither is later digitally subtracted from the output code [69] or pushed out of the band using oversampling [70].…”

Section: Introductionmentioning

confidence: 99%

“…The added dither is later digitally subtracted from the output code [69] or pushed out of the band using oversampling [70]. Different from equalization and dithering, a bottom-up weight calibration technique proposed in Chapter 5 is employed in this work.…”

Section: Introductionmentioning

confidence: 99%

“…Though regenerative latch is commonly used as the comparator for moderateresolution SAR ADCs [46,49], the noise requirement on high-resolution comparators makes a single latch difficult to accomplish the task. Averaging the comparison result for noise-sensitive conversion steps has been utilized to enhance the accuracy of the latch, but this approach only helps the ADC to achieve SNDR up till 70dB [69,70]. In this work, a single-pole amplifier (SPA) with gain enhancement [63] is used as a pre-amplification stage before the dynamic latch.…”

Section: Introductionmentioning

confidence: 99%

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Ultra-Low-Power Analog-to-Digital Converters for Medical Applications

Zhang

2014

Linköping Studies in Science and Technology. Dissertations

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Biomedical systems are commonly attached to or implanted into human bodies, and powered by harvested energy or small batteries. In these systems, analog-to-digital converters(ADCs) are key components as the interface between the analog world and the digital domain. Conversion of the low frequency bioelectric signals does not require high speed, but ultra-low-power operation. This combined with the required conversion accuracy makes the design of such ADCs a major challenge. Among prevalent ADC architectures, the successive-approximation-register (SAR) ADC exhibits significantly high energy efficiency due to its good trade-offs among power consumption, conversion accuracy, and design complexity. This thesis examines the physical limitations and investigates the design methodologies and circuit techniques for low-speed and ultra-low-power SAR ADCs.The power consumption of SAR ADC is analyzed and its lower bounds are formulated in the thesis. At low resolutions, power is bounded by minimum feature sizes; while at medium to high resolutions, power is bounded by thermal noise and capacitor mismatch. In order to relax the mismatch requirement on the capacitor sizing while still ensuring enough linearity for high resolution, a bottom-up weight calibration technique is further proposed. It utilizes redundancy generated by a non-binary-weighted capacitive network, and measures the actual weights of more significant capacitors using less significant capacitors.Three SAR ADCs have been implemented. The first ADC, fabricated in a 0.13µm CMOS process, achieves 9.1ENOB with 53-nW power consumption at 1kS/s. The main key to achieve the ultra-low-power operation turns out to be the maximal simplicity in the ADC architecture and low transistor count. In addition, a dual-supply voltage scheme allows the SAR digital logic to operate at 0.4V, reducing the overall power consumption of the ADC by 15% without any loss in performance. Based on the understanding from the first ADC and motivated by the predicted power bounds, the second ADC, a single-supply 9.1-ENOB SAR ADC in 65nm CMOS process has been further fabricated. It achieves a substantial (94%) improvement in power consumption with 3-nW total power at 1kS/s and 0.7V. Following the same concept of imposing maximal simplicity in the ADC architecture and taking advantage of the smaller feature size, the ultra-low-power consumption is achieved by a matched splitiv array capacitive DAC, a bottom-plate full-range input-sampling scheme, a latch-based SAR control logic, and a multi-V T design approach. The third ADC fabricated in 65nm CMOS process targets at a higher resolution of 14b and a wider bandwidth of 5KHz. It achieves 12.5ENOB with 1.98-µW power consumption at 0.8V and 10kS/s. To achieve the high resolution, the ADC implements a uniform-geometry non-binaryweighted capacitive DAC and employs a secondary-bit approach to dynamically shift decision levels for error correction. Moreover, a comparator with bias control utilizes the redundancy to reduce the power consumption....

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“…Even though the SAR ADC is renowned for its excellent power efficiency at moderate resolutions [2], the design of SAR ADCs with effective number of bits (ENOB) above 12 bits [1,[3][4][5] poses formidable challenges due to the requirements on comparator noise and capacitor matching. The pipelined SAR ADC also known as the SAR-assisted pipeline ADC harnesses the advantages of SAR and pipelined ADCs to realize high resolution and improved sampling rate.…”

mentioning

confidence: 99%

Design of a 12.8 ENOB, 1 kS/s pipelined SAR ADC in 0.35-μm CMOS

Chen

Harikumar

Alvandpour

2015

Analog Integr Circ Sig Process

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This paper presents a 15-bit, two-stage pipelined successive approximation register (SAR) analog-to-digital converter (ADC) suitable for low-power, cost-effective sensor readout circuits. The use of aggressive gain reduction in the residue amplifier combined with a suitable capacitive array DAC topology in the second stage simplifies the design of the operational transconductance amplifier (OTA) while eliminating excessive capacitive load and consequent power consumption. An elaborate power consumption analysis of the entire ADC was performed to determine the number of bits in each stage of the pipeline. Choice of a segmented capacitive array DAC and attenuation capacitor-based DAC for the first and second stages respectively enable significant reduction in power consumption and area. Fabricated in a low-cost 0.35-µm CMOS process, the prototype ADC achieves a peak SNDR of 78.9 dB corresponding to an effective number of bits (ENOB) of 12.8 bits at a sampling frequency of 1 kS/s and provides an FoM of 157.6 dB. Without any form of calibration, the ADC maintains an ENOB > 12.1 bits upto the Nyquist bandwidth of 500 Hz while consuming 6.7 µW. Core area of the ADC is 0.679 mm 2 .

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A 71dB-SNDR 50MS/s 4.2mW CMOS SAR ADC by SNR enhancement techniques utilizing noise

Cited by 48 publications

References 2 publications

A 14-bit 10kS/s power efficient 65nm SAR ADC for cardiac implantable medical devices

A 14-bit 10kS/s power efficient 65nm SAR ADC for cardiac implantable medical devices

Ultra-Low-Power Analog-to-Digital Converters for Medical Applications

Design of a 12.8 ENOB, 1 kS/s pipelined SAR ADC in 0.35-μm CMOS

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