A 77-dB Dynamic Range, 7.5-MHz Hybrid Continuous-Time/Discrete-Time Cascaded $\Sigma \Delta$ Modulator

Kulchycki, S.D.; Trofin, Roxana; Vleugels, K.; Wooley, B.A.

doi:10.1109/jssc.2008.917499

Cited by 62 publications

(25 citation statements)

References 18 publications

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“…Ideally, the modulator is able to digitize signals with B w from 5MHz to 60MHz and an effective resolution ranging from 9 to 16 bits. According to (8), these specifications can be satisfied for OSR 1 ∈ [8,128] and p = [2,3,4,5,6]. This is illustrated in Fig.…”

Section: Finite Gbw Errormentioning

confidence: 97%

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Efficient Multi-rate Hybrid Continuous-Time/Discrete-Time Cascade 2-2 Sigma-Delta Modulators for Wideband Telecom

Garcia-Sanchez

Rosa

2012

VLSI-SoC: Advanced Research for Systems on Chip

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Abstract. This chapter discusses the use of hybrid continuous-time /discrete-time fourth-order cascade two-stage 2-2 ΣΔ modulators for wideband low-power wireless applications. The modulator architecture under study is based on a new concept of multi-rate operation, in which the front-end stage -implemented using continuous-time (Gm-C) integrators -operates at a higher rate than the back-end (switched-capacitor) stage. This strategy benefits from the faster operation of continuous-time circuits while keeping power efficiency and high robustness against circuit element tolerances. A comparison with conventional multi-rate and single-rate (continuous-time) ΣΔ modulators is carried out based on the impact of main circuit-level error mechanisms, namely: mismatch, finite OTA dc gain and finite gain-bandwidth product. Closed-form analytical expressions are derived for the nonideal in-band noise power of the different architectures under study, demonstrating a good agreement with simulations and showing the benefits of the presented approach. Simulation results show that the proposed modulator is able to operate with a maximum sampling rate of up to 1GHz, digitizing signals with a 44-to-92dB peak signal-to-(noise+distortion) ratio within a programmable 5-to-60MHz bandwidth.

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Section: Finite Gbw Errormentioning

confidence: 97%

“…In these hybrid topologies some parts of the modulator -usually the front-end blocks -are implemented with CT circuits, thus benefiting from their faster operation, embedded anti-aliasing filtering and reduced power dissipation, while keeping a higher robustness against circuit errors than in pure CT-ΣΔMs [2][3][4][5][6].…”

Section: Introductionmentioning

confidence: 99%

Efficient Multi-rate Hybrid Continuous-Time/Discrete-Time Cascade 2-2 Sigma-Delta Modulators for Wideband Telecom

Garcia-Sanchez

Rosa

2012

VLSI-SoC: Advanced Research for Systems on Chip

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“…Therefore, the input-signal level can exceed . In this case, only the second part of (3) is relevant where is substituted by , the maximum input into the modulator is given by (8) Substituting (4) into (8) and solving for , the maximum input-signal level can be determined: (9) Equation (9) holds as long as the inter-stage gain is bounded by (7).…”

Section: -Mash Modulatormentioning

confidence: 99%

“…In previous implementations, cascades of ( MASH) and cascades of followed by a zero-order quantizer ( -0 MASH, also known as the Leslie-Singh architecture [2]) have been reported. Examples of MASH include discrete-time implementations [3]- [5], a continuous-time implementation [6], and a hybrid continuous-time/discrete-time realization [7].…”

Section: Introductionmentioning

confidence: 99%

A 12-bit 3.125-MHz bandwidth 0-3 MASH delta-sigma modulator

Gharbiya

Johns

2008

ESSCIRC 2008 - 34th European Solid-State Circuits Conference

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Abstract-We demonstrate a 12-bit 0-3 MASH delta-sigma modulator with a 3.125 MHz bandwidth in a 0.18 m CMOS technology. The modulator has an oversampling ratio of 8 (clock frequency of 50 MHz) and achieves a peak SNDR of 73.9 dB (77.2 dB peak SNR) and consumes 24 mW from a 1.8 V supply. For comparison purposes, the modulator can be re-configured as a single-loop topology where a peak SNDR of 64.5 dB (66.3 dB peak SNR) is obtained with 22 mW power consumption. The energy required per conversion step for the 0-3 MASH architecture (0.95 pJ/step) is less than half of that required by the feedback topology (2.57 pJ/step).

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“…Several modulators targeting 10-12 bit resolutions with signal bandwidths in the 5-20 MHz range have been reported. Most designs reported in 0.18 lm CMOS achieve about 10 bit resolution over a signal bandwidth of 10 MHz or lesser (see for example [1,2]), with an exception being [3], where time-interleaved techniques were used to achieve a resolution of approximately 8 bits over a 20 MHz bandwidth. Most converters with bandwidths in excess of 10 MHz have been implemented in processes with a minimum feature size of 0.13 lm or smaller [4][5][6].…”

Section: Introductionmentioning

confidence: 99%

A power efficient continuous time ΔΣ modulator with 15 MHz bandwidth and 70 dB dynamic range

Reddy

Pavan

2009

Analog Integr Circ Sig Process

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We present architectural and circuit details of a high speed continuous-time DR modulator operating at a sampling rate of 300 Msps in a 0.18lm CMOS process. A large quantizer range of 2.4 V (peak-to-peak differential) reduces thermal noise requirements of the loop filter and matching requirements in the flash ADC. Active-RC techniques are used in the loop filter, and excess loop delay compensation circuitry mitigates the effect of finite bandwidth of the opamps and feedback DAC delay. Thanks to the design techniques employed, the modulator achieves a peak SNR of 67.2 dB in a 15 MHz bandwidth (OSR = 10) while dissipating 20.7 mW from a 1.8 V supply.

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A 77-dB Dynamic Range, 7.5-MHz Hybrid Continuous-Time/Discrete-Time Cascaded $\Sigma \Delta$ Modulator

Cited by 62 publications

References 18 publications

Efficient Multi-rate Hybrid Continuous-Time/Discrete-Time Cascade 2-2 Sigma-Delta Modulators for Wideband Telecom

Efficient Multi-rate Hybrid Continuous-Time/Discrete-Time Cascade 2-2 Sigma-Delta Modulators for Wideband Telecom

A 12-bit 3.125-MHz bandwidth 0-3 MASH delta-sigma modulator

A power efficient continuous time ΔΣ modulator with 15 MHz bandwidth and 70 dB dynamic range

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