A power efficient continuous time ΔΣ modulator with 15 MHz bandwidth and 70 dB dynamic range

Abstract

We present architectural and circuit details of a high speed continuous-time DR modulator operating at a sampling rate of 300 Msps in a 0.18lm CMOS process. A large quantizer range of 2.4 V (peak-to-peak differential) reduces thermal noise requirements of the loop filter and matching requirements in the flash ADC. Active-RC techniques are used in the loop filter, and excess loop delay compensation circuitry mitigates the effect of finite bandwidth of the opamps and feedback DAC delay. Thanks to the design techniques employed, the modulator achieves a peak SNR of 67.2 dB in a 15 MHz bandwidth (OSR = 10) while dissipating 20.7 mW from a 1.8 V supply.

Multi-bit continuous-time delta-sigma modulator for audio application

“…However, a current steering DAC [19] shown in figure 8 greatly reduces the slew requirement of first op-amp in the loop-filter which improves the stability of the system [17] has been designed for a current of 1 uA. The DWA has been implemented by a 4 layer barrel shifter method [20].…”