There has been an increased demand for 3G cell phones that support multiple bands of operation and are backward compatible with the 2G/2.5G standard to provide coverage where 3G networks have not yet been fully deployed. The transceiver design for such a handset becomes complicated with the need for separate transceivers for 3G and 2G/2.5G [1,2] or for multiple inter-stage receive / transmit SAW filters [3]. A single-chip transceiver that operates as a multimode multiband radio and eliminates the inter-stage receive / transmit SAW filters is presented. Figure 6.3.1 shows the block diagram of the transceiver with 7 primary and 4 diversity bands in WCDMA, and quad band in GSM. The transceiver is designed to operate in any of the UTRA bands 1 to 10, with the exception of band 7. It supports HSDPA (Cat 1-12), HSUPA (Cat 1-6), EGPRS (Classes 1-12, 30-39), and compressed mode of EGPRS / WCDMA operation. The transceiver is compliant with 3G DigRF interface 3.09.The analog / RF section of the transmitter is shown in Fig. 6.3.2. The I/Q DAC is based on oversampled current steering with 10b accuracy realized with a 6b-unary and 4b-binary segmentation. The output of the DAC is fed to a 3 rdorder Chebyshev continuous-time filter that attenuates out-of-band noise and DAC images and drives the I/Q modulator. The filter can be configured to operate in WCDMA, GMSK or EDGE mode. The I/Q modulator is a passive LO-2LO mixer. Two levels of passive switches are driven by LO and 2×LO frequencies with proper phases. This mixer configuration achieves both lower phase noise in the LO path and isolation between I and Q baseband inputs, and addresses the stringent linearity and noise requirements of GSM/WCDMA. The differential output of the I/Q modulator is converted to single-ended output using an on-chip balun. The balun output is then amplified in the driver stage and sent off-chip to the PA. The transmitter provides 80dB of gain-control range in WCDMA mode and 40dB in EDGE mode. The gain control is distributed across the chain and designed to meet the linearity and noise requirements over power-control range, while optimizing the current consumption. At high power (24 to 0dBm) a closed-loop power control scheme in the transceiver is used for accurate power control, and at lower power (0 to -57dBm) a conventional power-control scheme through the base-station is used.The architecture of the receiver front-end is shown in Fig. 6.3.3. The mixers and LO buffers are shared among several LNAs to reduce die area. The mixer outputs are connected to the virtual grounds created by the transimpedance amplifiers (TIAs) and its inputs are driven by the output current from the LNA. In this current-driven passive-mixer topology, the voltage swings at the mixer input and output are significantly reduced, resulting in improved linearity. In a passive mixer design, the noise contribution of the TIA increases as the impedance at the mixer input decreases. Therefore, an LC tank is used at the LNA cascode output with switchable capacitors to adjust the tan...

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This paper presents the design of a second order, single bit, CMOS, continuous-time analog to digital delta sigma modulator (ΔΣΜ) which samples at 2 GHz, consumes 18 mW at 1.8 V and has a 79 dB signal-to-noise ratio (SNR) over a 1.23 MHz bandwidth. Because the comparator s metastability limited the ΔΣΜ s performance, this paper focuses on the design, analysis and testing of the ΔΣΜ s comparator. The ΔΣΜ s measured performance is also presented.

In this work, a power-area-efficient, 3-band, 2-RX MIMO, and TD-LTE (backward compatible with the HSPA+, HSUPA, HSDPA, and TD-SCDMA) CMOS receiver is presented and implemented in 0.13-μm CMOS technology. The continuous-time delta-sigma A/D converters (CT ΔΣ ADCs) are directly coupled to the outputs of the transimpedance amplifiers, eliminating the need of analog anti-aliasing filters between RX front-end and ADCs in conventional structures. The strong adjacent channel interference without lowpass filter attenuation is handled by proper gain control. A low-power small-area solution for excess loop delay compensation is implemented in the CT ΔΣ ADC. At 20 MHz bandwidth, the CT ΔΣ ADC achieves 66 dB dynamic range and 3.5 dB RX chip noise figure is measured. A maximum of 2.4 dB signal-to-noise ratio degradation is measured in all the adjacent channel selectivity (ACS) and blocking tests, demonstrating the effectiveness of the strategy against the low-pass filter removal from the conventional architecture. The receiver dissipates a maximum of 171 mW at 2-RX MIMO mode. To our best knowledge, it is the first research paper on the design of fully integrated commercial TD-LTE receiver.

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