A 2-GHz analog-to-digital delta-sigma modulator for CDMA receivers with 79-dB signal-to-noise ratio in 1.23-MHz bandwidth

Dagher, Elias H.; Stubberud, Peter; Masenten, W. K.; Conta, M.; Dinh, Thanh Vinh

doi:10.1109/jssc.2004.835831

Cited by 24 publications

(10 citation statements)

References 9 publications

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“…Indeed, the effect of metastability is a critical issue as the clock frequency increases and the timing errors become limiting factors. However, the use of multiple latches has been demonstrated very effective even for sampling frequencies in the GHz range [93].…”

Section: B Circuit Errors In Msmentioning

confidence: 99%

Sigma-Delta Modulators: Tutorial Overview, Design Guide, and State-of-the-Art Survey

Rosa

2011

IEEE Trans. Circuits Syst. I

195

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Section: B Circuit Errors In Msmentioning

confidence: 99%

Sigma-Delta Modulators: Tutorial Overview, Design Guide, and State-of-the-Art Survey

Rosa

2011

IEEE Trans. Circuits Syst. I

195

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“…However, in spite of the mentioned advantages, the majority of reported H-! "M ICs [5]- [10] do not really exploit the capability of CMOS CT circuits to operate up to the GHz range with reasonable linearity [11], and hence to significantly increase the digitized signal bandwidth with medium-high values of OSR. This is due to the fact that the maximum sampling rate of H-!…”

Section: Introductionmentioning

confidence: 99%

Multirate hybrid CT/DT cascade ΣΔ modulators with decreasing OSR of back-end DT stages

Garcia-Sanchez

Rosa

2010

Proceedings of 2010 IEEE International Symposium on Circuits and Systems

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This paper presents novel architectures of multirate hybrid cascade continuous-time/discrete-time !" modulators that take advantage of the potentially faster operation of the continuoustime part of the circuit, while keep a reduced sampling operation of the back-end discrete-time stages. Compared to conventional multirate !" modulators, the proposed architectures use a higher sampling rate in the front-end (continuous-time) stage of the modulator, whereas the back-end (discrete-time) stages operate at a lower rate. It is demonstrated that the intrinsic aliasing signal can be cancelled in the digital domain, with no additional analog hardware required. The resulting !" topologies are potentially faster than conventional multirate !" modulators, more power efficient than hybrid monorate architectures and more robust than cascade continuous-time implementations. The combination of these features results in a new class of !" modulators, very suited for the implementation of analog-to-digital converters in the next generation of broadband wireless telecom systems.

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“…These technologies allow sampling at high frequencies (5 GHz and beyond) at the expense of power consumption. Recent DR modulators are integrated using low-cost CMOS technologies in order to reduce power consumption [6]. To improve both stability and SNR of DR modulators, multi-bit quantizer is used instead of the usual 1-bit quantizer [7].…”

Section: Introductionmentioning

confidence: 99%

Design of a high-speed CMOS multi-bit quantizer for continuous-time Delta-Sigma Modulator applications

Mariano

Goumballa

Dallet

et al. 2008

Analog Integr Circ Sig Process

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Digital front-end receivers realize direct conversion of an analog signal to digital form at intermediate frequencies (IF), simplifying the overall system design and alleviating the problems associated with IF mixers. The trend is to eliminate any RF/analog mixers and digitize the RF signal as near as possible to the antenna. In order to digitize directly the analog input signal, a high dynamic-range and high-speed ADC is needed. Continuous-Time Bandpass Delta-Sigma Modulator can meet these requirements, using high-performance multi-bit quantizers. This article presents the design of a high-speed CMOS Analog-to-Digital Converter (ADC) which can be used as a quantizer in Continuous-Time Delta-Sigma Modulator. It is designed in a 130 nm CMOS technology from STMicroelectronics. The main features of the ADC are 3-bit resolution with 4 GHz sampling rate in a 0.8-2 GHz bandwidth.

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A 2-GHz analog-to-digital delta-sigma modulator for CDMA receivers with 79-dB signal-to-noise ratio in 1.23-MHz bandwidth

Cited by 24 publications

References 9 publications

Sigma-Delta Modulators: Tutorial Overview, Design Guide, and State-of-the-Art Survey

Sigma-Delta Modulators: Tutorial Overview, Design Guide, and State-of-the-Art Survey

Multirate hybrid CT/DT cascade ΣΔ modulators with decreasing OSR of back-end DT stages

Design of a high-speed CMOS multi-bit quantizer for continuous-time Delta-Sigma Modulator applications

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A 2-GHz analog-to-digital delta-sigma modulator for CDMA receivers with 79-dB signal-to-noise ratio in 1.23-MHz bandwidth

Cited by 24 publications

References 9 publications

Sigma-Delta Modulators: Tutorial Overview, Design Guide, and State-of-the-Art Survey

Sigma-Delta Modulators: Tutorial Overview, Design Guide, and State-of-the-Art Survey

Multirate hybrid CT/DT cascade &#x03A3;&#x0394; modulators with decreasing OSR of back-end DT stages

Design of a high-speed CMOS multi-bit quantizer for continuous-time Delta-Sigma Modulator applications

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Multirate hybrid CT/DT cascade ΣΔ modulators with decreasing OSR of back-end DT stages