No abstract

In this work, a power-area-efficient, 3-band, 2-RX MIMO, and TD-LTE (backward compatible with the HSPA+, HSUPA, HSDPA, and TD-SCDMA) CMOS receiver is presented and implemented in 0.13-μm CMOS technology. The continuous-time delta-sigma A/D converters (CT ΔΣ ADCs) are directly coupled to the outputs of the transimpedance amplifiers, eliminating the need of analog anti-aliasing filters between RX front-end and ADCs in conventional structures. The strong adjacent channel interference without lowpass filter attenuation is handled by proper gain control. A low-power small-area solution for excess loop delay compensation is implemented in the CT ΔΣ ADC. At 20 MHz bandwidth, the CT ΔΣ ADC achieves 66 dB dynamic range and 3.5 dB RX chip noise figure is measured. A maximum of 2.4 dB signal-to-noise ratio degradation is measured in all the adjacent channel selectivity (ACS) and blocking tests, demonstrating the effectiveness of the strategy against the low-pass filter removal from the conventional architecture. The receiver dissipates a maximum of 171 mW at 2-RX MIMO mode. To our best knowledge, it is the first research paper on the design of fully integrated commercial TD-LTE receiver.

No abstract

No abstract

INTRODUCTIONThe UHF Adaptive Array Processor was developed as a research tool for the design of a fleet deployable adaptive antenna system for naval communications. It s u p p r e s s e s j a m m e r s and interfergain in the direction of desired signals. The array processor erence on UHF communications channels and provides maximum values to form beams and nulls in the directions of the desired accomplishes t h i s by adaptively setting the antenna element weight signal and interference, respectively. Measured values of the with the array output provide a vector input to the processor weight cross covariance of each antenna element signal (hard limited) control subsystem to effect the adaptive feedback control. The functional design of the UHF Adaptive Array Processor and the hardware implementation are described. Test results with a four element communications antenna are presented. The test results demonstrate the performance of the processor with spread specnarrowband 2nd wideband jammers and multipath environments. trum communication signals being received in the presence of 2. FUiTCTIONAL DESIGN OF THE UHF ADAPTIVE ARRAY PROCESSOR tion of S / N and S/I power ratios by using only measurements ofThe design of the adaptive a r r a y processor allows the maximizacross covariance estimates. This approach has enough versatility to p e r m i t a variety of current mean square adaptation algorithms to be implemented via software without requiring hardware changes. The functional design shown in Figure 1 is the approach selected to accomplish this goal. Based on the concept of measuring only the time average estimates of the wjde and narrow baxd signal cross covariance vectors R(k) and Q(k), respectively, this design avoids the problems (throughput and s a m p l i n g r a t e s ) of processing wideband data.In the UHF adaptive array processor the output of the pattern forming network is ?(t) = ET (k)g(t)(1)where W(k) is the complex weighting vector [constant in the time interval (k-1) AT to kb T 1 and z(t) is the complex envelope of X ( t ) 3 94