A 7nm CMOS platform technology featuring 4<sup>th</sup> generation FinFET transistors with a 0.027um<sup>2</sup> high density 6-T SRAM cell for mobile SoC applications

Wu, Shien‐Yang; Lin, Chih‐Yu; Chiang, Meng-Hsueh; Liaw, J.J.; Cheng, J.Y.; Yang, Shixuan; Tsai, C.S.; Chen, P.N.; Miyashita, T.; Chang, Chih-Hsien; Chang, V.S.; Pan, K.H.; Chen, J.H.; Mor, Y. S.; Lai, K.T.; Liang, C.S.; Chen, H.F.; Chang, Shau-Feng; Lin, Chung-Kai; Hsieh, C.H.; Tsui, R.F.; Yao, C.H.; Chen, C.C.; Chen, R.; Lee, C.H.; Lin, Hon-Jarn; Chang, Chi Cheng; Chen, K.W.; Tsai, Ming-Hsien; Chen, K.S.; Ku, Yao-Ching; Jang, S. M.

doi:10.1109/iedm.2016.7838333

Cited by 109 publications

(49 citation statements)

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“…Thin-film technology is inexpensive per unit area compared to traditional silicon, but this advantage can be offset by the increase in area. The smallest SRAM cell in thin-film technology shown today is 0.6mm² as presented by Geier et al [10], compared to 0.027µm² for the most recent 7nm CMOS technology [12]. For most envisioned applications, at least 1kb memory is needed.…”

Section: About Here]mentioning

confidence: 99%

A Thin-Film, a-IGZO, 128b SRAM and LPROM Matrix With Integrated Periphery on Flexible Foil

Roose

Myny

Ameys

et al. 2017

IEEE J. Solid-State Circuits

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A fast, 128 bit implementation of both SRAM and LPROM with integrated periphery in a thin-film a-IGZO technology is reported. The SRAM block can be read in 265µs/byte and written in 110µs/byte, consumes 12.3mWand has an area of 11.9mm². Furthermore, after power down an SRAM memory state retention time of 83s is shown.The LPROM can be read in 40µs/bit, consumes 4.50mW and has an area of 3.75mm². The SRAM enables fast volatile RAM memory for thin-film microprocessors, while the LPROM can be used to store the identification code for state-of-the-art thin-film RFID tags.

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Section: About Here]mentioning

confidence: 99%

A Thin-Film, a-IGZO, 128b SRAM and LPROM Matrix With Integrated Periphery on Flexible Foil

Roose

Myny

Ameys

et al. 2017

IEEE J. Solid-State Circuits

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“…inFET transistors with outstanding electrical transport behavior in 14nm CMOS technology have been successfully demonstrated in high-volume production for low power and high performance applications [1]- [4]. High drive current combined with low power consumption, as well as simplified fabrication process with minimized impact on intrinsic silicon electrical properties have become mainstream in today's semiconductor industry.…”

Section: Introductionmentioning

confidence: 99%

Electrical Characteristics of LDD and LDD-Free FinFET Devices of Dimension Compatible With 14 nm Technology Node

Hassan

Zhao

et al. 2020

IEEE J. Electron Devices Soc.

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FinFET devices with and without LDD implantation has been studied for dimensions compatible with leading 14nm technology node. Devices without LDD have better electrostatic characteristics with SS = 65mV/dec and DIBL = 33mV. The nFET transistors with no LDD have device Vtsat mismatch reduction by 20%, together with retained device reliability of HCI as compared to devices with LDD. A full range of device Vtsat flavors is enabled in this experiment, presenting excellent device performances at different operating voltages of 0.55V, 0.8V and 1.2V. All results indicates that devices with no LDD and one less mask in FinFET architecture achieve lower cost, compelling performance and area scaling compared to devices with LDD, for high performance and low power applications.

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“…However under the umbrella of Internet of Things (IoT) and Internet of Everything (IoE) a big variety of applications pop up, in order to satisfy the people's needs in transportation, health-care, manufacturing, and energy management with diverse requirements, which traditional SoCs are not always capable to support due to the cost of semiconductor processing and fabrication and the complexity in terms of the amount of circuit elements for a large die. At the same time the smallest features of transistors reached 7nm [25] and IMEC manufactured first 3nm transistor [6]. Furthermore a huge increase in Integrated Circuits (IC) cost is observed.…”

Section: Introductionmentioning

confidence: 99%

MicroLET: A New SDNoC-Based Communication Protocol for ChipLET-Based Systems

Ellinidou

Sharma

Kontogiannis

et al. 2019

2019 22nd Euromicro Conference on Digital System Design (DSD)

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Currently the industry moves to smaller process nodes even if the cost for yielding large dies continues to increase, moving to the 5nm and even 3nm nodes. Hence a chipletbased design has been initiated and quickly gain attention from industry, academia and government agencies. This cutting edge approach became advantageous to break down a large die into smaller chiplets in order to improve yield and binning. In order to exploit this new approach the interconnect fabric connecting the nodes of the entire system should be of high importance to enable the properly distribution of the data. Each individual chiplet may contain its own local Network on Chip (NoC), which operates for intra-chiplet traffic. However the communication over chipletbased systems is complicated enough, due to various routing algorithms and NoC topologies and an alternative solution is needed. In this paper we introduce an SDNoC(Software Define Network on Chip)-based communication protocol for chipletbased systems, called MicroLET, which consists of a flexible and modular SDNoC architecture and 3 main phases: Handshake, Network Monitoring, Routing. An implementation of the SDNoC architecture and an evaluation of the proposed routing algorithm compared to the XY and the Odd-Even algorithms within different traffic scenarios is presented. Through the evaluation of the MicroLET protocol, it is proven that it could be a good candidate for the future chiplet-based systems.

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A 7nm CMOS platform technology featuring 4^th generation FinFET transistors with a 0.027um² high density 6-T SRAM cell for mobile SoC applications

Cited by 109 publications

References 0 publications

A Thin-Film, a-IGZO, 128b SRAM and LPROM Matrix With Integrated Periphery on Flexible Foil

A Thin-Film, a-IGZO, 128b SRAM and LPROM Matrix With Integrated Periphery on Flexible Foil

Electrical Characteristics of LDD and LDD-Free FinFET Devices of Dimension Compatible With 14 nm Technology Node

MicroLET: A New SDNoC-Based Communication Protocol for ChipLET-Based Systems

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A 7nm CMOS platform technology featuring 4th generation FinFET transistors with a 0.027um2 high density 6-T SRAM cell for mobile SoC applications

Cited by 109 publications

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A Thin-Film, a-IGZO, 128b SRAM and LPROM Matrix With Integrated Periphery on Flexible Foil

A Thin-Film, a-IGZO, 128b SRAM and LPROM Matrix With Integrated Periphery on Flexible Foil

Electrical Characteristics of LDD and LDD-Free FinFET Devices of Dimension Compatible With 14 nm Technology Node

MicroLET: A New SDNoC-Based Communication Protocol for ChipLET-Based Systems

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A 7nm CMOS platform technology featuring 4^th generation FinFET transistors with a 0.027um² high density 6-T SRAM cell for mobile SoC applications