-A process to make self-aligned top-gate amorphous indium-gallium-zinc-oxide (a-IGZO) thin-film transistors (TFTs) on polyimide foil is presented. The source/drain (S/D) region's parasitic resistance reduced during the SiN interlayer deposition step. The sheet resistivity of S/D region after exposure to SiN interlayer deposition decreased to 1.5 kΩ/□. TFTs show field-effect mobility of 12.0 cm 2 /(V.s), sub-threshold slope of 0.5 V/decade, and current ratio (I ON/OFF ) of >10 7. The threshold voltage shifts of the TFTs were 0.5 V in positive (+1.0 MV/cm) bias direction and 1.5 V in negative (À1.0 MV/cm) bias direction after extended stressing time of 10 4 s. We achieve a stage-delay of~19.6 ns at V DD = 20 V measured in a 41-stage ring oscillator. A top-emitting quarter-quarter-video-graphics-array active-matrix organic light-emitting diode display with 85 ppi (pixels per inch) resolution has been realized using only five lithographic mask steps. For operation at 6 V supply voltage (V DD ), the brightness of the display exceeds 150 cd/m 2 .

We present a qHD (960 × 540 with three sub‐pixels) top‐emitting active‐matrix organic light‐emitting diode display with a 340‐ppi resolution using a self‐aligned IGZO thin‐film transistor backplane on polyimide foil with a humidity barrier. The back plane process flow is based on a seven‐layer photolithography process with a CD = 4 μm. We implement a 2T1C pixel engine and use a commercial source driver IC made for low‐temperature polycrystalline silicon. By using an IGZO thin‐film transistor and leveraging the extremely low off current, we can switch off the power to the source and gate driver while maintaining the image unchanged for several minutes. We demonstrate that, depending on the image content, low‐refresh operation yields reduction in power consumption of up to 50% compared with normal (continuous) operation. We show that with the further increase in resolution, the power saving through state retention will be even more significant.

The maturity of metal-oxide thin-film transistors (TFT) highlights opportunities to develop robust and low-cost electronics on flexible and stretchable substrates over large area in an industry-compatible technology. Internet-of-Everything applications with sensor nodes are driving the development of analog-to-digital converters (ADCs). In this paper, a self-biased and self-digital-controlled successive approximation ADC with integrated references and sensor read-in circuitry together with a printed negative temperature coefficient (NTC) sensor using unipolar dual-gate metal-oxide (InGaZnO) TFTs is demonstrated. The system is operated at a clock of up to 400 Hz and a total power dissipation of 245 mW (73 µW from analog) at a maximum power supply of 30 V is measured. The radio-frequency identification-ready ADC comprises of a total of 1394 indium-gallium-zinc oxide TFTs and 31 metal-insulatormetal capacitors. A figure of merit of 26 nJ/c.s. is achieved from the ADC driven from external microcontroller. The robustness of the various blocks of the chip is characterized and the yield is discussed.

Flexible low-cost RFID/NFC tags have great potential to be embedded in everyday objects providing them a unique identifier or sensor readout facilitating the Internet-of-Everything, whereby a smartphone or tablet is the interface to the Internet-of-Things. The main challenge for flexible metal-oxide RFID tags is to fully comply with the ISO14443-A NFC standard to enable readout by standard NFC reader or handheld devices, due to the limited charge carrier mobility of the semiconductor and multiple sources of parameter variation caused by roughness, temperature and dimensional stability of the foils. Recent work by various groups [1][2][3][4] demonstrated only an incremental improvement in data rates from 50b/s to 396.5kb/s to be compatible with ISO14443 (105.9kb/s). In this work, we present a flexible metal-oxide NFC chip that is compliant with ISO14443-A, showcasing advancements on memory size, power consumption and a clock generation circuit.The flexible self-aligned metal-oxide transistor technology is shown in Fig. 15.2.1. The semiconductor is Indium-Gallium-Zinc-Oxide (IGZO) resulting in n-type thinfilm transistors (TFTs) exhibiting a mobility of 13.49cm²/Vs. The cross-section details a scalable self-aligned transistor architecture with channel lengths down to 2 and 1.5μm, and polyimide as flexible substrate. The gate insulator is 100nm SiO 2 . 400nm SiN x serves as decoupling layer between the metallization layers to decrease the parasitic overlap capacitors and acts as doping layer for the semiconductor area, which is not covered by gate dielectric. The local V T variability of 2μm self-aligned TFTs on flex is 150mV (Fig. 15. 2.1).The ISO14443-A specification describes a bit representation with data rates of 105.9kb/s (13.56MHz carrier divided by 128), Manchester encoding and OOK subcarrier modulation with a clock of 847.5kHz (carrier divided by 16). The logic gate delay to enable clock division is targeted around 10× of the carrier frequency, being 7.37ns. The spec on gate delay is studied by integrating unipolar n-type, pseudo-CMOS inverters [5] into 19-stage ring oscillators. The effect of channel length scaling on the inverter performance is plotted in Fig. 15.2.2, resulting obtained stage delays of 63.4ns for L=5μm and 5.2ns for L=2μm at 5V VDD and 10V VBIAS. In addition, the transistor ratios of the VBIAS branch have been adapted featuring a faster implementation of the pseudo-CMOS inverter (L2F and L1.5F). This reduces the stage delay down to 2.36ns at 5V VDD and 10V VBIAS for the 1.5μm version. Figure 15.2.2 shows that this logic implementation meets the specification for all VDD variations, yielding a more robust division circuit. The clock division circuit is based on negative edge-triggered flipflops. Figure 15.2.2 depicts also the measured clock division range for VDD varying between 3V to 5V. As expected, the 1.5μm fast implementation can divide a 13.56MHz signal over this supply range, with a maximum operating frequency of 27.3MHz.The drawback of channel length scaling without decreasing the...

A fast, 128 bit implementation of both SRAM and LPROM with integrated periphery in a thin-film a-IGZO technology is reported. The SRAM block can be read in 265µs/byte and written in 110µs/byte, consumes 12.3mWand has an area of 11.9mm². Furthermore, after power down an SRAM memory state retention time of 83s is shown.The LPROM can be read in 40µs/bit, consumes 4.50mW and has an area of 3.75mm². The SRAM enables fast volatile RAM memory for thin-film microprocessors, while the LPROM can be used to store the identification code for state-of-the-art thin-film RFID tags.