A 90nm 512mb 166MHz multilevel cell flash memory with 1.5MByte/s programming

Taub, M.; Bains, R.; Barkley, G.; Castro, H.A.; Christensen, G.; Eilert, Sean; Fackenthal, R.; Giduturi, H.; Goldman, M.; Haid, C.; Haque, Rezaul; Parat, Krishna; Peterson, Scott; Proescholdt, A.; Ramamurthi, K.; Ruby, P.; Smidt, A.; Srinivasan, Balaji; Szwarc, M.; Tedrow, K.; Young, D.

doi:10.1109/isscc.2005.1493865

Cited by 15 publications

(2 citation statements)

References 4 publications

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“…V wl,step1 is the incremental gate voltage in the first step ( V wl,step1 ≥ 1 V). V wl,step2 is the incremental gate voltage in the second step, and given by V w1,step2 = V th,target − V th,fgbl (8) V th,fgbl = 25% × α fgbl V th,pg2 (9) where V th,fgbl is the V th shift because of FG-to-FG coupling interference through the two sides of C fgbl from the neighboring cells, and α fgbl is FG-to-FG coupling ratio between a memory cell and the two sides of neighboring cells in the BL direction (α fgbl = 0.032 for a virtual ground). N p is reduced from 44 to 16 cycles for virtual-ground memory, from (5)- (9).…”

Section: E Comparison Of Pt For Virtual-ground and Standard Nor Flasmentioning

confidence: 99%

Scalable Virtual-Ground Multilevel-Cell Floating-Gate Flash Memory

Yamauchi

Kamakura

Matsuoka

2013

IEEE Trans. Electron Devices

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An adequate gate coupling ratio (GCR) and compensation for floating-gate to floating-gate (FG-to-FG) coupling interference must be maintained to enable further scaling of virtual-ground multilevel-cell (MLC) FG flash memory. A high GCR of 0.6 is obtained using a novel bowl-shaped FG structure cell technology without sacrificing cell size. Increasing the GCR is important for reducing FG-to-FG coupling interference and achieving low-voltage operation. A novel array segmented virtualground architecture with bit-line isolation between neighboring segments and two-step programming with the channel hot electron injection threshold voltage compensation technique are proposed to reduce the number of neighboring cells that are programmed after programming a given cell, as well as the amount of threshold voltage (V th ) shift of the neighboring cells. Adoption of this programming approach realizes a reduction in the V th shift caused by the FG-to-FG coupling interference < 25% in the bit-line direction, compared with conventional programming approaches, and the V th shift is almost completely eliminated in the word-line direction without sacrificing program throughput. The proposed virtual-ground MLC FG cell, which is as small as 3F 2 /bit (F is the minimum feature size) is successfully implemented into a test chip with good reliability.

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Section: E Comparison Of Pt For Virtual-ground and Standard Nor Flasmentioning

confidence: 99%

Scalable Virtual-Ground Multilevel-Cell Floating-Gate Flash Memory

Yamauchi

Kamakura

Matsuoka

2013

IEEE Trans. Electron Devices

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“…Multi-level cell (MLC) storage technology is widely used to increase density and lower product cost. As a result, improvement of the program throughput has become a hot topic in NOR MLC design [2,3] .…”

Section: Introductionmentioning

confidence: 99%

Temperature self-adaptive program algorithm on 65 nm MLC NOR flash memory

Shi

Hong

Hu³

et al. 2009

J. Semicond.

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This paper presents an implementation for improving muti-level cell NOR flash memory program throughput based on the channel hot electron (CHE) temperature characteristic. The CHE Ig temperature characteristic is analyzed theoretically with the Lucky electron model, and a temperature self-adaptive programming algorithm is proposed to increase Ig according to the on-die temperature. Experimental results show that the program throughput increases significantly from 1.1 MByte/s without temperature self-adaptive programming to 1.4 MByte/s with the proposed method at room temperature. This represents a 30% improvement and is 70 times faster than the program throughput in Ref. [1].

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A scalable stepped gate sensing scheme for sub-100nm multilevel flash memory

Bauer

Tedrow

2005

2005 International Conference on Integrated Circuit Design and Technology, 2005. ICICDT 2005.

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A 90nm 512mb 166MHz multilevel cell flash memory with 1.5MByte/s programming

Cited by 15 publications

References 4 publications

Scalable Virtual-Ground Multilevel-Cell Floating-Gate Flash Memory

Scalable Virtual-Ground Multilevel-Cell Floating-Gate Flash Memory

Temperature self-adaptive program algorithm on 65 nm MLC NOR flash memory

A scalable stepped gate sensing scheme for sub-100nm multilevel flash memory

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