Scalable Virtual-Ground Multilevel-Cell Floating-Gate Flash Memory

Abstract

An adequate gate coupling ratio (GCR) and compensation for floating-gate to floating-gate (FG-to-FG) coupling interference must be maintained to enable further scaling of virtual-ground multilevel-cell (MLC) FG flash memory. A high GCR of 0.6 is obtained using a novel bowl-shaped FG structure cell technology without sacrificing cell size. Increasing the GCR is important for reducing FG-to-FG coupling interference and achieving low-voltage operation. A novel array segmented virtualground architecture with bit-line isolation between neighboring segments and two-step programming with the channel hot electron injection threshold voltage compensation technique are proposed to reduce the number of neighboring cells that are programmed after programming a given cell, as well as the amount of threshold voltage (V th ) shift of the neighboring cells. Adoption of this programming approach realizes a reduction in the V th shift caused by the FG-to-FG coupling interference < 25% in the bit-line direction, compared with conventional programming approaches, and the V th shift is almost completely eliminated in the word-line direction without sacrificing program throughput. The proposed virtual-ground MLC FG cell, which is as small as 3F 2 /bit (F is the minimum feature size) is successfully implemented into a test chip with good reliability.

Review on Non-Volatile Memory with High-k Dielectrics: Flash for Generation Beyond 32 nm

“…A relatively thick tunneling oxide and inter poly dielectric layer have to be used in the floating-gate memory to maintain acceptable reliability, limiting further down-scaling of the cell size in the vertical direction [4]. In addition, maintaining a high gate coupling ratio is still one main bottle-neck for down-scaling the floating-gate devices [5]. Moreover, as the spacing between adjacent devices is down-scaled, this parasitic capacitance plays an increasingly dominant role in the device performance due to data stored in the adjacent cells can interfere with each other by capacitive coupling [6].…”

N2 gas flow rate dependence on the high-k LaB x N y thin film characteristics formed by RF sputtering for floating-gate memory applications

“…10,11) The nonvolatile memory devices with low power, highspeed operation, and large storage are widely investigated such as metal/oxide/nitride/oxide/silicon (MONOS) structure and floating-gate type devices. [12][13][14][15][16][17] In the conventional floating-gate memory device, the high-k insulator for tunnel layer (TL) and block layer (BL) and a metal layer for floating gate (FG) and control gate (CG) are widely studied to improve the memory characteristics. [17][18][19][20][21][22] However, the high operation voltage (>10 V) is necessary.…”

In situ formation of Hf-based metal/oxide/nitride/oxide/silicon structure for nonvolatile memory application

“…[1][2][3] Recently, conventional floating gate (FG)-type NVM devices in large-scale integrated circuits (LSIs) are facing scaling limits in terms of coupling ratio and disturbance between cells among others. [4][5][6][7] Charge-trapping (CT)-type NVM devices such as metal=oxide=nitride=oxide= silicon (MONOS) or silicon=oxide=nitride=oxide=silicon (SONOS) are attractive candidates for realizing further scaling down. [8][9][10][11][12][13][14] For low-voltage operation, CT-type NVM devices with various high-k dielectrics were investigated, such as HfLaON=HfON=SiO 2 =Si and Al=Al 2 O 3 =ZrON=SiO 2 =Si.…”