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In this study, we investigated the electrical characteristics of a Hf-based metal/oxide/nitride/oxide/silicon (MONOS) nonvolatile memory (NVM) device formed in situ for the first time. Furthermore, the effects of the in situ HfN gate stack formation process on the electrical characteristics of the Hf-based MONOS device were also investigated by comparing with the device with the Al gate formed ex situ. The drain-current–gate-voltage (ID–VG) characteristics with negligible hysteresis and high yield were realized by using the in situ HfN gate. A memory window (MW) as large as 4.2 V was obtained at the program voltage/time (VPGM/tPGM) of 10 V/1 s and the erase voltage/time (VERS/tERS) of −10 V/1 s. Furthermore, the low-voltage and short-pulse operations, such as ±6 V/2 ms were achieved. Finally, 2-bit/cell operation of the Hf-based MONOS device was demonstrated for the first time utilizing electron injection at the source and drain regions.

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Variability improvement of metal-oxidesemiconductor field-effect transistors (MOSFETs) characteristics with high-k HfON gate insulator by Si surface flattening was investigated. The Si surface flattening process was carried out by Ar/4.9%H2 anneal utilizing rapid thermal annealing (RTA) system. The HfON gate insulator was formed by the in-situ Ar/O2 plasma oxidation of HfN utilizing electron cyclotron resonance (ECR) plasma sputtering followed by the post deposition anneal (PDA) at 600 o C for 1 min. The Si surface flattening was found to significantly improve the threshold voltage variability (VTH) of MOSFET with HfON gate insulator for the first time. Furthermore, the stability of the device characteristics was improved up to the measurement temperature of 100 o C by introducing the Si surface flattening process. Index Terms-ECR plasma sputtering, gate insulator, HfON, high-k, MOSFETs, Si surface flattening, variability 0894-6507 (c)