2018
DOI: 10.1587/transele.e101.c.328
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Improvement of Endurance Characteristics for Al-Gate Hf-Based MONOS Structures on Atomically Flat Si(100) Surface Realized by Annealing in Ar/H<sub>2</sub> Ambient

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Cited by 10 publications
(11 citation statements)
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“…10,15,21) The equivalent oxide thickness (EOT) was calculated as 7.0 nm for HfO 2 TL and 5.2 nm for HfON TL MONOS structure. [14][15][16][17][18][19][20][21] SiO 2 has a lower relative dielectric constant (ε SiO2 ∼ 3.9) than HfO 2 (ε HfO 2 ∼ 20) and HfON (ε HfON ∼ 21). 21,22) Previously, 2-bit/cell operation of HfO 2 TL was investigated at a V PGM /t PGM of 6 V/2 ms, with V DS = 1.5 V. 10,19) The calculated effective field stress in the TL is 8.6 MV/cm at V PGM of 6 V in the case of HfO 2 TL.…”
Section: Resultsmentioning
confidence: 99%
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“…10,15,21) The equivalent oxide thickness (EOT) was calculated as 7.0 nm for HfO 2 TL and 5.2 nm for HfON TL MONOS structure. [14][15][16][17][18][19][20][21] SiO 2 has a lower relative dielectric constant (ε SiO2 ∼ 3.9) than HfO 2 (ε HfO 2 ∼ 20) and HfON (ε HfON ∼ 21). 21,22) Previously, 2-bit/cell operation of HfO 2 TL was investigated at a V PGM /t PGM of 6 V/2 ms, with V DS = 1.5 V. 10,19) The calculated effective field stress in the TL is 8.6 MV/cm at V PGM of 6 V in the case of HfO 2 TL.…”
Section: Resultsmentioning
confidence: 99%
“…Furthermore, we have reported the excellent electrical characteristics of a Hf-based MONOS structure formed in situ by ECR plasma sputtering with a HfO 2 and HfON tunneling layer (TL). 10,[14][15][16][17][18][19][20][21] The composition of each layer was reported, and it is designed using the reported results, previously. 10) In the case of HfO 2 , the SiO 2 interfacial layer (IL) is formed between the TL and Si substrate which increased the equivalent oxide thickness (EOT) and degraded operation speed.…”
Section: Introductionmentioning
confidence: 99%
“…13) These processes would cause the degradation of interface properties because of contamination at each interface of the MONOS structures. [14][15][16][17][18][19] With device scaling, low-frequency noise (LFN) such as 1/f noise and random telegraph noise (RTN) becomes important in the investigation of interface characteristics of memory devices. [20][21][22][23][24][25][26][27][28] Because the number of stored electrons is reduced by the scaling down of devices, a single CT/charge de-trapping induces a significant fluctuation in the drain current (I D ).…”
Section: Introductionmentioning
confidence: 99%
“…[3][4][5][6][7][8][9][10] We have reported the Hf-based MONOS NVM with high-k HfO 2 and HfN 1.1 dielectrics. [11][12][13][14][15][16][17] The Hf-based MONOS structures were fully in situ formed to improve the interface property by the reactive sputtering utilizing Hf target. The MONOS structures are consisted from HfN 0.5 gate electrode, HfO 2 blocking layer (BL), HfN 1.1 charge trapping layer (CTL), HfO 2 tunneling layer (TL), and we have demonstrated the multibit/cell operation.…”
Section: Introductionmentioning
confidence: 99%