In situ formation of Hf-based metal/oxide/nitride/oxide/silicon structure for nonvolatile memory application

Abstract

In this study, we investigated the electrical characteristics of a Hf-based metal/oxide/nitride/oxide/silicon (MONOS) nonvolatile memory (NVM) device formed in situ for the first time. Furthermore, the effects of the in situ HfN gate stack formation process on the electrical characteristics of the Hf-based MONOS device were also investigated by comparing with the device with the Al gate formed ex situ. The drain-current–gate-voltage (ID–VG) characteristics with negligible hysteresis and high yield were realized by using the in situ HfN gate. A memory window (MW) as large as 4.2 V was obtained at the program voltage/time (VPGM/tPGM) of 10 V/1 s and the erase voltage/time (VERS/tERS) of −10 V/1 s. Furthermore, the low-voltage and short-pulse operations, such as ±6 V/2 ms were achieved. Finally, 2-bit/cell operation of the Hf-based MONOS device was demonstrated for the first time utilizing electron injection at the source and drain regions.

Multi-level 2-bit/cell operation utilizing Hf-based metal/oxide/nitride/oxide/silicon nonvolatile memory with HfO2 and HfON tunneling layer

“…9) This process would cause the degradation of interface characteristics because of the contamination at each interface of the MONOS structure during the transfer of the wafers, and it would lead to the degradation of device characteristics. 10) To achieve low-voltage operation for MONOS NVM devices, a MONOS structure with excellent interface property is necessary.…”

“…Furthermore, we have reported the excellent electrical characteristics of a Hf-based MONOS structure formed in situ by ECR plasma sputtering with a HfO 2 and HfON tunneling layer (TL). 10,[14][15][16][17][18][19][20][21] The composition of each layer was reported, and it is designed using the reported results, previously. 10) In the case of HfO 2 , the SiO 2 interfacial layer (IL) is formed between the TL and Si substrate which increased the equivalent oxide thickness (EOT) and degraded operation speed.…”

“…10,[14][15][16][17][18][19][20][21] The composition of each layer was reported, and it is designed using the reported results, previously. 10) In the case of HfO 2 , the SiO 2 interfacial layer (IL) is formed between the TL and Si substrate which increased the equivalent oxide thickness (EOT) and degraded operation speed. [19][20][21] Meanwhile, HfON suppresses the SiO 2 IL growth.…”

HfN multi charge trapping layers for Hf-based metal-oxide-nitride-oxide-Si nonvolatile memory

“…[3][4][5][6][7][8][9][10] We have reported the Hf-based MONOS NVM with high-k HfO 2 and HfN 1.1 dielectrics. [11][12][13][14][15][16][17] The Hf-based MONOS structures were fully in situ formed to improve the interface property by the reactive sputtering utilizing Hf target. The MONOS structures are consisted from HfN 0.5 gate electrode, HfO 2 blocking layer (BL), HfN 1.1 charge trapping layer (CTL), HfO 2 tunneling layer (TL), and we have demonstrated the multibit/cell operation.…”

“…However, the threshold voltage (V TH ) controllability was necessary to be improved. 15) The possible method to improve the MONOS characteristics is the use of high-k multi CTL. Tang et al reported that the multi CTL formed by the multi Zr silicate layers to improve the MONOS characteristics.…”