A 90nm CMOS power amplifier for 802.16e (WiMAX) applications

Degani, Ofir; Cossoy, Fabian; Shahaf, Shay; Chowdhury, Debopriyo; Hull, Christopher; Cohen, E.; Ravid, Shmuel

doi:10.1109/rfic.2009.5135561

Cited by 15 publications

(3 citation statements)

References 17 publications

(8 reference statements)

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“…In [5], 32.8dBm linear output power is achieved at 2.45GHz but LDMOS devices are used for the design of the power amplifier instead of standard devices. In [6], a CMOS power amplifier has been designed for WLAN application in 90nm CMOS process to achieve 32dBm-saturated power at 3.3V supply. However, transformer based power combining is used which leads to high load sensitivity.…”

Section: Introductionmentioning

confidence: 99%

A CMOS power amplifier with 180° hybrid on-chip coupler for 4G applications

Arrawatia

Baghini

Kumar

2015

2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS)

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This paper presents a CMOS Class AB power amplifier with an on-chip 180 • hybrid coupler for 4G applications. Two-stage power amplifier architecture with a combination of low voltage core transistor and high voltage I/O transistors, is designed to achieve the power gain in the 180nm standard CMOS technology. The driver stage has a power gain of 18.5dB and linear output power of 12.9dBm. The power stage has a gain of 13.7dB and P 1dB of 24.4dBm. The paper also presents an onchip 180 • hybrid coupler, designed in the same technology, for combining the power generated from individual power amplifiers. The measured results of the coupler show an isolation better than -30dB, S11 better than -20dB and, S21 and S31 equal to -5.4dB, at 2.35GHz. The complete differential power amplifier using the on-chip coupler gives P 1dB of 26.4dBm and saturated output power of 27.4dBm. As compared to all the reported onchip couplers configurations, use of 180 • hybrid coupler leads to better load insensitivity as well as improved linearity due to the second harmonic cancellation.

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Section: Introductionmentioning

confidence: 99%

A CMOS power amplifier with 180° hybrid on-chip coupler for 4G applications

Arrawatia

Baghini

Kumar

2015

2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS)

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“…In Ref. [4] a single stage 90 nm CMOS PA integrated with a balun is reported having 18 dB gain and 32 dBm saturated power (P sat /. Furthermore, digital pre-distortion technology is used to enhance PA linearity.…”

Section: Introductionmentioning

confidence: 99%

A fully integrated 3.5 GHz CMOS differential power amplifier driver

Yang

Hongfeng

2013

J. Semicond.

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A fully integrated CMOS differential power amplifier driver (PAD) is proposed for WiMAX applications. In order to fulfill the differential application requirements, a transmission line transformer is used as the output matching network. A differential inductance constitutes an inter-stage matching network. Meanwhile, an on chip balun realizes input matching as well as single-end to differential conversion. The PAD is fabricated in a 0.13 m RFCMOS process. The chip size is 1.1 1.1 mm 2 with all of the matching network integrated on chip. The saturated power is around 10 dBm and power gain is about 12 dB.

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“…Recently, with the demand of a single‐chip transceiver and cost pressure in volume production, CMOS power amplifier (PA)has been studied intensively [1–3]. A transformer is an essential element for implementation of a fully integrated CMOS PA because it can successfully solve the source inductance problem by offering an RF virtual ground and boost the load impedance level [4].…”

Section: Introductionmentioning

confidence: 99%

A compact broadband transformer‐based linear CMOS power amplifier design

Jin

Zhao

Kim

2010

Micro & Optical Tech Letters

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the isolation characteristic, as shown in Figure 6(b). Tables 1 and 2 show the measured antenna efficiencies t various gap distances and interconnection positions. As the maximum value available for h is limited to 3 mm, we chose the gap distance between two boards to be 3 mm. The results reveal that the efficiency of the proposed MIMO antenna is dependent upon the isolation between the two radiating elements.Figures 7(a)-7(f) show three-dimensional (3D) radiation patterns of the designed two radiating elements at 750, 880, and 1920 MHz, respectively. Although the laptop structure affects the radiation pattern, especially in low band, the measured radiation patterns are nearly omnidirectional over most of the frequency band. Figure 8 shows the measured antenna gain and the envelope correlation coefficient (ECC) as a function of frequency. The average gains of the two antenna elements are shown as short dashed and dashed-dotted lines, and the ECC is drawn as a solid line in Figure 8. The gain varies from~À6.7 dBi to À1.7 dBi, and the ECC is mostly lower than 0.35 across the entire bandwidth. Although the MIMO antenna is installed within an electrically small USB dongle device, the proposed internal MIMO antenna can achieve good gain and ECC performances using the two-stage ground. The mean effective gain (MEG) values vary from 0.28 to 0.47 over the entire bandwidth, as shown in Figure 9. CONCLUSIONSA compact internal MIMO antenna with a separated two-stage ground is proposed. The two radiating elements in the MIMO antenna have good performance and a wide bandwidth for wireless communications (LTE, DCN, and PCS-1900). Although the two elements are embedded in a USB dongle and operate at low frequency (LTE band), good isolation and relatively high antenna efficiency were achieved by using a two-stage ground structure. The proposed antenna is a superior candidate for future wireless applications due to its capability to fit within a USB dongle terminal. ABSTRACT: A novel broadband transformer-based CMOS power amplifier (PA) design method is studied in this article. To obtain a broadband PA, the parasitic parameters of the transformer are absorbed into the PAs load match and their impacts on bandwidth are studied. The fully-integrated PA combined with an 8-shaped transformer is implemented in 0.13 lm CMOS process with only 1.2 Â 1.2 mm 2 chip size and operates at Class AB mode. The single-stage PA delivers 27.36 dBm output power with 27% efficiency and has 10.5 dB gain. It has 500 MHz bandwidth (1 dB degeneration) in the large and small signal measurements. IMD3 and IMD5 are also lower than À25 dBc at 19 dBm across the bandwidth. The spectrum of PA can meet the m-WiMAX spectrum mask at 19 dBm average power level.

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A 90nm CMOS power amplifier for 802.16e (WiMAX) applications

Cited by 15 publications

References 17 publications

A CMOS power amplifier with 180° hybrid on-chip coupler for 4G applications

A CMOS power amplifier with 180° hybrid on-chip coupler for 4G applications

A fully integrated 3.5 GHz CMOS differential power amplifier driver

A compact broadband transformer‐based linear CMOS power amplifier design

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A 90nm CMOS power amplifier for 802.16e (WiMAX) applications

Cited by 15 publications

References 17 publications

A CMOS power amplifier with 180&#x00B0; hybrid on-chip coupler for 4G applications

A CMOS power amplifier with 180&#x00B0; hybrid on-chip coupler for 4G applications

A fully integrated 3.5 GHz CMOS differential power amplifier driver

A compact broadband transformer‐based linear CMOS power amplifier design

Contact Info

Product

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A CMOS power amplifier with 180° hybrid on-chip coupler for 4G applications

A CMOS power amplifier with 180° hybrid on-chip coupler for 4G applications