A &amp;#x0394;&amp;#x03A3; fractional-N synthesizer with customized noise shaping for WCDMA/HSDPA applications

Xiang, Yu; Sun, Yun; Rhee, Woogeun; Wang, Zhihua; Ahn, Hyung Ki; Park, Byeong-Ha

doi:10.1109/cicc.2008.4672196

Cited by 9 publications

(5 citation statements)

References 10 publications

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“…Furthermore, this solution can be used to make present multistandard synthesizers cover WCDMA band VII, since usually only the LO's for the lower bands are generated. In any case, the power penalty of 6 mW seems definitely reasonable, considering that GSM and GSM/WCDMA synthesizers typically dissipate several tens of milliwatts [14][15][16][17][18][19]. From the perspective of area consumption, the overhead of the proposed multiplier is totally negligible: as a matter of fact, the proposed circuit is based on digital gates and the area consumption will be dominated by the passive components of the loop filter of Fig.…”

Section: Resultsmentioning

confidence: 99%

A local oscillator for WCDMA band VII based on frequency multiplication

Gerosa

Bevilacqua

Neviani

2012

Analog Integr Circ Sig Process

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This work explores the generation of a local oscillator for WCDMA band VII based on frequency multiplication of a GSM reference. The frequency multiplier is based on a PLL, which includes a compact VCO based on a ring oscillator. A proper PLL design allows to sufficiently reject the relative high VCO phase noise, complying with the WCDMA requirements. The effectiveness of the proposed approach is proved with the design of the whole multiplier in a 90 nm CMOS technology. The generated oscillation ranges from 3 to 6 GHz, while the simulated phase noise is −120 and −144 dBc/Hz at a frequency offset of 0.6 and 20 MHz, respectively, dissipating 6.3 mW

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Section: Resultsmentioning

confidence: 99%

A local oscillator for WCDMA band VII based on frequency multiplication

Gerosa

Bevilacqua

Neviani

2012

Analog Integr Circ Sig Process

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“…The transfer function of the hybrid FIR filter can be designed regardless of the PLL loop dynamics, thus a customized quantization noise shaping is possible. In other words, phase noise at certain frequency can be suppressed more by introducing the zero of the FIR filter at that frequency [6]. Since the FIR filtering is effective only on the MMD control path but not on the PLL small signal path, it suppresses the ΔΣ modulator noise without affecting the PLL loop dynamics.…”

Section: A Review Of Hybrid Fir Filtering Methodsmentioning

confidence: 98%

A latency-proof quantization noise reduction method for digitally-controlled ring oscillators

Liu

Rui

Xiang

et al. 2010

2010 53rd IEEE International Midwest Symposium on Circuits and Systems

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This paper describes a quantization noise reduction method for ΔΣ based digitally-controlled ring oscillators (DCRO). A concept of the hybrid finite-impulse response (FIR) filter from the fractional-N PLL is extended to the DCRO design. Thanks to the parallel operation, the proposed filter based noise reduction method does not cause any additional latency to the digital PLL. Both behavioral and circuit-level simulations are performed, showing that out-of-band phase noise or short-term jitter caused by the ΔΣ modulator can be significantly reduced with the proposed method.

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“…The VCO differential output is sent to the sequent MMD and compared to the reference clock. Figure 10 shows phase shifter (PS) based MMD [ 9 , 14 ] module to provide a programmable division ratio of 64–127 controlled by the baseband phase signal via the DSM. The high frequency current-mode-logic (CML) divider with a fixed division ratio of 4 generates quadrature output phases, which are shaped to nonoverlapping quadrature clocks to ease the timing requirement of logic circuits and are fed into eight parallel PS-based MMDs with 4-stage single-ended 2/3 prescalers supporting the division ratio of 16–31.…”

Section: Design Implementationsmentioning

confidence: 99%

“…Considering that fewer DSM output levels result in smaller instantaneous phase error at the PFD output and thus less phase noise, and on the other hand, the wider DSM output levels have more efficient randomization and dithering and generate less fractional spurs to the PLL [ 15 ], the DSM employs 4th-order single-loop architecture [ 14 ] as the trade-off between in-band noise and fractional spurs.…”

Section: Design Implementationsmentioning

confidence: 99%

A Low-Noise Delta-Sigma Phase Modulator for Polar Transmitters

Zhou

2014

The Scientific World Journal

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A low-noise phase modulator, using finite-impulse-response (FIR) filtering embedded delta-sigma (ΔΣ) fractional-N phase-locked loop (PLL), is fabricated in 0.18 μm CMOS for GSM/EDGE polar transmitters. A simplified digital compensation filter with inverse-FIR and -PLL features is proposed to trade off the transmitter noise and linearity. Experimental results show that the presented architecture performs RF phase modulation well with 20 mW power dissipation from 1.6 V supply and achieves the root-mean-square (rms) and peak phase errors of 4° and 8.5°, respectively. The measured and simulated phase noises of −104 dBc/Hz and −120 dBc/Hz at 400-kHz offset from 1.8-GHz carrier frequency are observed, respectively.

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A ΔΣ fractional-N synthesizer with customized noise shaping for WCDMA/HSDPA applications

Cited by 9 publications

References 10 publications

A local oscillator for WCDMA band VII based on frequency multiplication

A local oscillator for WCDMA band VII based on frequency multiplication

A latency-proof quantization noise reduction method for digitally-controlled ring oscillators

A Low-Noise Delta-Sigma Phase Modulator for Polar Transmitters

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