A Binary Tree Based Methodology for Designing an Application Specific Network-on-Chip (ASNOC)

Jeang, Yuan-Long

doi:10.1093/ietfec/e88-a.12.3531

“…Jeang et al present both a potential NoC platform as well as a design approach for said platform in [41). The proposed NoC architecture is a hybrid design, incorporating both local interconnects in the form of buses, cross-bars or multi-layer interconnects, as well as NoC switches for communication amongst local networks.…”

Section: Binary Tree Hybrid Noc Designsmentioning

confidence: 99%

Network-On-Chip Topology Generation and Analysis For Transaction-Based Systems-on-Chip

Dumitriu¹

2021

Preprint

0

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The Network-on-Chip concept is emerging as a promising new method of addressing the communication requirements of complex Systems-on-Chip. However, network design at this level must take into consideration the specific communication protocols of on-chip components. This thesis presents a topology analysis and design method for networks-on-chip based on the transaction-oriented protocols common to on-chip systems. The generated topologies target the latency of critical links in the system, while the analysis method can predict the degree of contention in a system prior to the simulation phase. The proposed topologies are tested using various applications, including and MPEG4 Decoder, and are found to perform the same or better than regular topologies, while using less network resources. The contention prediction method is found to be accurate to within 27% in the worst case scenario.

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“…Jeang et al present both a potential NoC platform as well as a design approach for said platform in [41). The proposed NoC architecture is a hybrid design, incorporating both local interconnects in the form of buses, cross-bars or multi-layer interconnects, as well as NoC switches for communication amongst local networks.…”

Section: Binary Tree Hybrid Noc Designsmentioning

confidence: 99%

Network-On-Chip Topology Generation and Analysis For Transaction-Based Systems-on-Chip

Dumitriu¹

2021

Preprint

0

View full text Add to dashboard Cite

The Network-on-Chip concept is emerging as a promising new method of addressing the communication requirements of complex Systems-on-Chip. However, network design at this level must take into consideration the specific communication protocols of on-chip components. This thesis presents a topology analysis and design method for networks-on-chip based on the transaction-oriented protocols common to on-chip systems. The generated topologies target the latency of critical links in the system, while the analysis method can predict the degree of contention in a system prior to the simulation phase. The proposed topologies are tested using various applications, including and MPEG4 Decoder, and are found to perform the same or better than regular topologies, while using less network resources. The contention prediction method is found to be accurate to within 27% in the worst case scenario.

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“…Folded torus reduces delay in torus [12]. Binary tree interconnection architecture [14] is popular, because it maintains hierarchical property for better management. But it has small bisection width.…”

Section: Related Workmentioning

confidence: 99%

Performance evaluation of a novel Dimension Order Routing algorithm for Mesh-of-tree based Network-on-Chip architecture

Manna

¹

,

Chattopadhyay

²

,

Gupta

³

2010

2010 First International Conference on Parallel, Distributed and Grid Computing (PDGC 2010)

0

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This paper present a new dimension-oriented routing algorithm for Mesh-of-tree (MoT) based Network-on-Chip (NoC) architecture. The addressing scheme is considerably simplified that enables us to reduce the minimum flit-size to 16-bits, compared to 32-bits in the previously reported works. The same level of throughput and average latency could be achieved with a 43.86% reduction in area and 43% reduction in energy. Bandwidth can be increased via increasing flit size. The design of the new router enables us to select routers of various complexities with performance trade-offs required for real-life application.

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A Binary Tree Based Methodology for Designing an Application Specific Network-on-Chip (ASNOC)

Cited by 12 publications

References 17 publications

Network-On-Chip Topology Generation and Analysis For Transaction-Based Systems-on-Chip

Network-On-Chip Topology Generation and Analysis For Transaction-Based Systems-on-Chip

Network-On-Chip Topology Generation and Analysis For Transaction-Based Systems-on-Chip

Performance evaluation of a novel Dimension Order Routing algorithm for Mesh-of-tree based Network-on-Chip architecture

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