This paper presents an efficient pipeline architecture to perform gray-scale morphologic operations. The features of the architecture are 1) lower hardware cost, 2) faster operation time in processing an image. 3) lower data access times from the image memory, 4) shorter latency, 5) suitability for VLSI implementation, and 6 ) adaptability for N*N morphologic operations.

The rearrangement of mirror elements has been presented. By virtue of the proposed approach, new topologies realizing the same transfer function as the initial circuit can be obtained. Moreover, we may derive the circuits with improved properties than the original circuit. A practical example has been given to demonstrate the feasibility.

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SUMMARYA novel CMOS cascode current mirror configuration with enhanced input dynamic range is presented. The proposed mirror circuit combines the advantages of wide input swing, wide output swing and large output resistance capability, which make it attractive for practical application. Based on 0.18 m MOS model parameters, HSPICE simulation results show that the input current ranges from 1 A to 1 mA with large bandwidth for the proposed circuit. The simulation results confirm the theoretical prediction.

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