A data-reuse architecture for gray-scale morphologic operations

Sheu, Ming‐Hwa; Wang, J.-F.; Chen, J.-S.; Suen, An-Nan; Jeang, Yuan-Long; Lee, J.-Y.

doi:10.1109/82.199903

Cited by 21 publications

(12 citation statements)

References 5 publications

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“…By Partial results reuse technique, first architecture is proposed by Sheu et al [3] in which partial results is generated for one operation and these results are reused by the later operation. This architecture is also called as PRR architecture which is called in [4].…”

Section: A Partial Results Reusementioning

confidence: 99%

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A Review on Parallel Implementation of Morphological Filter and Different Techniques

2017

IJAERD

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Section: A Partial Results Reusementioning

confidence: 99%

“…Here I is the input image of size KxL and B is the Structuring Element of size GxH which defines the size of the window. Mathematically, it can be expressed as: (3) In other terms, Erosion can be written as (4) where m is a set of point. So erosion is nothing but subtraction of pixels to the boundaries of object in the image.…”

Section: B Erosionmentioning

confidence: 99%

A Review on Parallel Implementation of Morphological Filter and Different Techniques

2017

IJAERD

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“…Only one-order PRR is considered in this technique, that is, all reused data are generated from the original data or only one reused data. For example, (12) and (13) are not equations of one-order PRR since two reused data are involved. The procedure involves three steps.…”

Section: B Arbitrary Structuring Elementsmentioning

confidence: 99%

“…It cannot be achieved without hardware accelerators. Many architectures for morphological operations have been proposed [9]- [13]. Loui et al [9] developed a flexible architecture for morphological image processing.…”

Section: Introductionmentioning

confidence: 99%

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Partial-result-reuse architecture and its design technique for morphological operations

Chien

Chen

2001 IEEE International Conference on Acoustics, Speech, and Signal Processing. Proceedings (Cat. No.01CH37221)

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Abstract-Mathematical morphology operations are applied in many real-time applications, such as video segmentation. For real-time requirement, efficient hardware implementation is necessary. This paper proposes a new architecture named Partial-Result-Reuse (PRR) architecture for mathematical morphological operations with flat structuring elements. Partial results generated during calculation process are kept and reused in this architecture to reduce hardware cost. With PRR concept and self-affinity property of structuring elements, the proposed architecture is more cost-effective and more general than existing morphology architectures. Moreover, it can be combined with systolic array to give consideration to both flexibility and hardware cost. We also propose a methodology to generate PRR architecture. With graphic method, the PRR architecture can be easily generated, and it can deal with structuring elements of any shape. The very large scale integration implementation of the PRR architecture shows that the area of processing element is small and can be fully piplelined without large overhead. The maximum frequency of the chip is 200 MHz in simulation, while processing speed of 550 morphological operations/s on a 720 480 frame can be achieved.

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Hybrid Morphology Processing Unit Architecture for Moving Object Segmentation Systems

Chien

Hsieh

Huang

et al. 2006

J VLSI Sign Process Syst Sign Image Video Technol

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Abstract. Video segmentation is a key operation in MPEG-4 content-based coding systems. For real-time applications, hardware implementation of video segmentation is inevitable. In this paper, we propose a hybrid morphology processing unit architecture for real-time moving object segmentation systems, where a prior effective moving object segmentation algorithm is implemented. The algorithm is first mapped to pixel-based operations and morphological operations, which makes the hardware implementation feasible. Then the high computation load, which is more than 4.2 GOPS, can be overcome with a dedicated morphology engine and a programmable morphology PE array. In addition, the hardware cost, memory size, and memory bandwidth can be reduced with the partial-result-reuse concept. This chip is designed with TSMC 0.35 µm 1P4M technology, and can achieve the processing speed of 30 QCIF frames or 7,680 morphological operations per second at 26 MHz. Simulation shows that the proposed hardware architecture is efficient in both hardware complexity and memory organization. It can be integrated into any content-based video processing and encoding systems.

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A data-reuse architecture for gray-scale morphologic operations

Cited by 21 publications

References 5 publications

A Review on Parallel Implementation of Morphological Filter and Different Techniques

A Review on Parallel Implementation of Morphological Filter and Different Techniques

Partial-result-reuse architecture and its design technique for morphological operations

Hybrid Morphology Processing Unit Architecture for Moving Object Segmentation Systems

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