Mesh-Tree Architecture for Network-on-Chip Design

Jeang, Yuan-Long; Wey, Tzuu-Shaang; Wang, Hung-Yu; Hung, Chung-Wei

doi:10.1109/icicic.2007.383

Cited by 5 publications

(2 citation statements)

References 4 publications

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“…It uses the mesh structure with a new diametrical link concept and reduces network diameter by 50% compared to 2D mesh. A new architecture called mesh-tree [5] which is a multilayered, 3-D, pyramidal topology, also been proposed. All topology structure described here shows mark able improvement over 2D mesh, but as the number of cores increases the performance degrades specially for diametrical 2D mesh.…”

Section: Background and Motivationmentioning

confidence: 99%

Diametric Mesh of Tree (DiaMoT) Routing Framework for High Performance NoCs: A Hierarchical Approach

Ghosal

Choudhuri

Rahaman

2012

2012 IEEE 14th International Conference on High Performance Computing and Communication &Amp; 2012 IEEE 9th International Confe

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Scalability issue is playing a very important role for the highly complex processing systems for the future generation of Network-on-Chips (NoCs). A large number of cores are connected to the communication fabric (router based network) using network interfaces inside an NoC. The problem complexity again increases with the increase in numbers of cores and components. Existing solutions can not be easily extended to solve this issue. In this paper, a new multilevel architecture for network on chip (NOC) and its corresponding deterministic routing is presented. This architecture is multilevel with each previous level structure used as a region in next level structure. So, there is a concept of reusing the previous structure. This topology structure gives smaller diameter and constant bisection width compared to mesh-of-tree and diametrical Mesh structure as the number of nodes grows. Meshof-tree and Diametrical Mesh give better performance compared to mesh structure. It is shown that our proposed topology structure gives better performance compared to the earlier methods. It is also proved that the proposed routing algorithm is deadlock free.

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Section: Background and Motivationmentioning

confidence: 99%

Diametric Mesh of Tree (DiaMoT) Routing Framework for High Performance NoCs: A Hierarchical Approach

Ghosal

Choudhuri

Rahaman

2012

2012 IEEE 14th International Conference on High Performance Computing and Communication &Amp; 2012 IEEE 9th International Confe

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“…Jeang et al [9] present a mesh pyramidal 3D NoC, where each layer is a mesh and trees connect adjacent layers. They optimize interlayer links enabling efficient broadcasting and high speed communications.…”

Section: Related Workmentioning

confidence: 99%

Tiny NoC: A 3D Mesh Topology with Router Channel Optimization for Area and Latency Minimization

Marcon

Fernandes

Cataldo

et al. 2014

2014 27th International Conference on VLSI Design and 2014 13th International Conference on Embedded Systems

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This paper presents Tiny NoC, which is a scalable and efficient 3D mesh architecture developed to minimize latency and NoC area. First, we show a theoretical analysis of latency and area occupancy to demonstrate Tiny NoC efficiency when compared to a basic mesh NoC. Then, we select a set of synthetic and mapping independent traffic with several injection rates to analyze the advantages and weaknesses of Tiny NoC. The experimental results highlight that Tiny NoC always reduces area occupancy and for several cases it provides latency minimization.

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De Bruijn graph based 3D Network on Chip architecture design

Chen

Ling

2009

2009 International Conference on Communications, Circuits and Systems

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Mesh-Tree Architecture for Network-on-Chip Design

Cited by 5 publications

References 4 publications

Diametric Mesh of Tree (DiaMoT) Routing Framework for High Performance NoCs: A Hierarchical Approach

Diametric Mesh of Tree (DiaMoT) Routing Framework for High Performance NoCs: A Hierarchical Approach

Tiny NoC: A 3D Mesh Topology with Router Channel Optimization for Area and Latency Minimization

De Bruijn graph based 3D Network on Chip architecture design

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