Tiny NoC: A 3D Mesh Topology with Router Channel Optimization for Area and Latency Minimization

Marcon, César; Fernandes, Ramon; Cataldo, Rodrigo; Grando, Fernando; Webber, Thais; Benso, Ana; Poehls, Leticia Bolzani

doi:10.1109/vlsid.2014.46

Cited by 12 publications

(5 citation statements)

References 16 publications

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“…TSVs prepare the communication connections between various layers. Due to very short connections, the 3D mesh network provides very small delay power and a wide bandwidth connection channel [31].…”

Section: Noc Topologiesmentioning

confidence: 99%

Towards Task Mapping Approaches in Network on Chips: A Comprehensive Survey

Màsdàrí

2023

Preprint

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One of the main stages of Network on Chip (NoC) is task mapping where the application tasks are mapped to the processing resources. Task mapping decisions have a direct impact on the NoC performance and can be classified as static or dynamic mapping methods. In this paper, we carry out a comprehensive systematic study of task mapping schemes in various NoCs. For this purpose, firstly, an overview of the task mapping's main concepts is presented. Then, a taxonomy of the mapping schemes regarding their objectives and applied mapping factors is presented and the studied schemes are categorized into fault-tolerant schemes, congestion-aware schemes, communication-aware approaches, temperature-aware methods, and energy-aware schemes. Afterward, their main contributions, provided services, and drawbacks of the proposed studies in the literature are illustrated. Moreover, a comprehensive discussion of various features of the investigated mapping methods is presented and issues such as the applied algorithms, simulators, datasets, and evaluation metrics are discussed. Finally, the concluding issues and open research areas are highlighted.

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Section: Noc Topologiesmentioning

confidence: 99%

Towards Task Mapping Approaches in Network on Chips: A Comprehensive Survey

Màsdàrí

2023

Preprint

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“…3D NoC has emerged as one of the compelling solutions to design high performance and energyefficient communication infrastructure for manycore chips. The natural extension of 2D planar architectures was the simple and regular 3D MESH-based NoC, which has been investigated in many existing works (Kim et al 2007;Marcon et al 2014). To exploit the advantages of TSV-based 3D integration, several works have addressed the synthesis of application-specific NoC architectures.…”

Section: Related Workmentioning

confidence: 99%

Performance and Thermal Tradeoffs for Energy-Efficient Monolithic 3D Network-on-Chip

Das

Doppa

Pande

et al. 2018

ACM Trans. Des. Autom. Electron. Syst.

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Three-dimensional (3D) integration enables the design of high-performance and energy-efficient network on chip (NoC) architectures as communication backbones for manycore chips. To exploit the benefits of the vertical dimension of 3D integration, through-silicon-via (TSV) has been predominantly used in state-of-the-art manycore chip design. However, for TSV-based systems, high power density and the resultant thermal hotspot remain major concerns from the perspectives of chip functionality and overall reliability. The power consumption and thermal profiles of 3D NoCs can be improved by incorporating a Voltage-Frequency-Island (VFI)-based power management strategy. However, due to inherent thermal constraints of a TSV-based 3D system, we are unable to fully exploit the benefits offered by the power management methodology. In this context, emergence of monolithic 3D (M3D) integration has opened up new possibility of designing ultra-low-power and high-performance circuits and systems. The smaller dimensions of the inter-layer dielectric (ILD) and monolithic inter-tier vias (MIVs) offer high-density integration, flexibility of partitioning logic blocks across multiple tiers, and significant reduction of total wire-length. In this work, we present the first-ever study of the performance-thermal tradeoffs for energy efficient monolithic 3D manycore chips. In particular, we present a comparative performance evaluation of M3D NoCs with respect to their conventional TSV-based counterparts. We demonstrate that the proposed M3D-based NoC architecture incorporating VFI-based power management achieves a maximum of 29.4% lower energy-delay-product (EDP) compared to the TSV-based designs for a large set of benchmarks. We also demonstrate that the M3D-based NoC shows up to 29.1% lower maximum temperature than the TSV-based counterpart for these benchmarks.

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“…Photonic interconnects offer high bandwidth and low power for future many-core chip design. A number of hybrid 3D/photonic NoC architectures have been designed [2] [19]. However, on-chip photonics still suffers from performance variation due to thermal issues [20].…”

Section: A 3d Noc Architectural Spacementioning

confidence: 99%

Design-Space Exploration and Optimization of an Energy-Efficient and Reliable 3-D Small-World Network-on-Chip

Das

Doppa

Pande

et al. 2017

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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A three-dimensional (3D) Network-on-Chip (NoC) enables the design of high performance and low power many-core chips. Existing 3D NoCs are inadequate for meeting the everincreasing performance requirements of many-core processors since they are simple extensions of regular 2D architectures and they do not fully exploit the advantages provided by 3D integration. Moreover, the anticipated performance gain of a 3D NoC-enabled many-core chip may be compromised due to the potential failures of through-silicon-vias (TSVs) that are predominantly used as vertical interconnects in a 3D IC. To address these problems, we propose a machine-learning-inspired predictive design methodology for energy-efficient and reliable many-core architectures enabled by 3D integration. We demonstrate that a small-world network-based 3D NoC (3D SWNoC) performs significantly better than its 3D MESH-based counterparts. On average, the 3D SWNoC shows 35% energydelay-product (EDP) improvement over 3D MESH for the PARSEC and SPLASH2 benchmarks considered in this work. To improve the reliability of 3D NoC, we propose a computationally efficient spare-vertical link (sVL) allocation algorithm based on a state-space search formulation. Our results show that the proposed sVL allocation algorithm can significantly improve the reliability as well as the lifetime of 3D SWNoC.

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Tiny NoC: A 3D Mesh Topology with Router Channel Optimization for Area and Latency Minimization

Cited by 12 publications

References 16 publications

Towards Task Mapping Approaches in Network on Chips: A Comprehensive Survey

Towards Task Mapping Approaches in Network on Chips: A Comprehensive Survey

Performance and Thermal Tradeoffs for Energy-Efficient Monolithic 3D Network-on-Chip

Design-Space Exploration and Optimization of an Energy-Efficient and Reliable 3-D Small-World Network-on-Chip

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