De Bruijn graph based 3D Network on Chip architecture design

Chen, Yiou; Hu, Jianhao; Ling, Xiang

doi:10.1109/icccas.2009.5250358

Cited by 10 publications

(4 citation statements)

References 6 publications

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“…The DB graph was also studied in the context of 3D NoCs. Chen et al [2009] proposed a partitioning into horizontal and vertical plane networks, in which both planes are DB graphs, along with a routing algorithm proposal that features lower latency than a 3D Mesh but higher power consumption.…”

Section: De Bruijn Graphsmentioning

confidence: 99%

A Survey on Design Approaches to Circumvent Permanent Faults in Networks-on-Chip

2016

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Increasing fault rates in current and future technology nodes coupled with on-chip components in the hundreds calls for robust and fault-tolerant Network-on-Chip (NoC) designs. Given the central role of NoCs in today's many-core chips, permanent faults impeding their original functionality may significantly influence performance, energy consumption, and correct operation of the entire system. As a result, fault-tolerant NoC design gained much attention in recent years. In this article, we review the vast research efforts regarding a NoC's components, namely, topology, routing algorithm, router microarchitecture, as well as system-level approaches combined with reconfiguration; discuss the proposed architectures; and identify outstanding research questions.

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Section: De Bruijn Graphsmentioning

confidence: 99%

A Survey on Design Approaches to Circumvent Permanent Faults in Networks-on-Chip

2016

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“…Chen et al [11] proposed a 3D NoC based on De Bruijn graph, whose architecture is called DB_DB. It is a topology with small diameter, simple routing and high reliability.…”

Section: Related Workmentioning

confidence: 99%

Tiny NoC: A 3D Mesh Topology with Router Channel Optimization for Area and Latency Minimization

Marcon

Fernandes

Cataldo

et al. 2014

2014 27th International Conference on VLSI Design and 2014 13th International Conference on Embedded Systems

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This paper presents Tiny NoC, which is a scalable and efficient 3D mesh architecture developed to minimize latency and NoC area. First, we show a theoretical analysis of latency and area occupancy to demonstrate Tiny NoC efficiency when compared to a basic mesh NoC. Then, we select a set of synthetic and mapping independent traffic with several injection rates to analyze the advantages and weaknesses of Tiny NoC. The experimental results highlight that Tiny NoC always reduces area occupancy and for several cases it provides latency minimization.

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“…Chen et al [11] introduced a new 3D NoC architecture based on De Bruijn graph, which is a topology with small diameter, simple routing and good reliability. Although the De Bruijn graphbased architecture can achieve smaller network latency than Mesh-based architectures, it has higher power consumption than Mesh topologies in most cases.…”

Section: Related Workmentioning

confidence: 99%

An asynchronous hierarchical router for networks‐on‐chip‐based three‐dimensional multi‐processor system‐on‐chip

2012

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SUMMARY Three‐dimensional networks‐on‐chip (3D NoC) are rising as a good approach to well managed complex interconnections in 3D multi‐processor system‐on‐chip (MPSoC). This paper introduces a new router in order to enhance throughput and latency compared to classic 3D mesh NoC. The proposed router is hierarchical as it is composed of two completely decoupled modules: one for inter‐layer communication and one for intra‐layer communication. It is fully implemented in asynchronous logic to allow low latency transfer. Synthesis and extrapolation results show that the hierarchical router is competitive with the classic 3D mesh in terms of area and power. Throughput and latency evaluation is performed using a SystemC‐TLM NoC simulator. Simulations' results show that the proposed hierarchical router can outperform the 3D mesh by more than 25% in terms of throughput and latency in the case of transpose traffic. Copyright © 2012 John Wiley & Sons, Ltd.

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De Bruijn graph based 3D Network on Chip architecture design

Cited by 10 publications

References 6 publications

A Survey on Design Approaches to Circumvent Permanent Faults in Networks-on-Chip

A Survey on Design Approaches to Circumvent Permanent Faults in Networks-on-Chip

Tiny NoC: A 3D Mesh Topology with Router Channel Optimization for Area and Latency Minimization

An asynchronous hierarchical router for networks‐on‐chip‐based three‐dimensional multi‐processor system‐on‐chip

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