A BIST Scheme for Bootstrapped Switches

Abstract

This paper proposes a built-in self-test (BIST) scheme for detecting catastrophic faults in bootstrapped switches. The clock signal and the gate voltage of the sampling MOS transistor are taken as the observation signals in the proposed BIST scheme. Usually, the gate voltage of the sampling MOS transistor is greater than or equal to the supply voltage when the switch is turn on, and such a voltage is not suitable for observation. To solve this problem, a low power supply voltage is provided for the bootstrapped switch to obtain a suitable observation voltage. The proposed BIST scheme and the circuit under test (CUT) are realized with transistor level. The proposed BIST scheme was simulated by HSPICE. The simulated fault coverage is approximately 87.9% with 66 test circuits.

A built-in self-test module for 16-bit parallel photon counting circuit using 180 nm CMOS process

“…In general, BIST scheme is replicated the function of ATE for error screening on circuit under test (CUT). BIST scheme is explicitly performed as fault diagnosis method for integrated digital module such multiplier chain, embedded memory and bootstrapped switches [9]. However, there are few works or findings on the fault diagnosis schemes for photon counter accumulator circuit, specifically can test the normal count and false count [6], [7].…”