A blind baud-rate ADC-based CDR

Abstract

ADC-based receivers process the received data in the digital domain, eliminating the need for much of the analog front end. In addition, a feed-forward blind architecture [1,2] eliminates the feedback loop between digital and analog domains so that the ADC and digital CDR can be designed and simulated independently. Previous works [1,2] sampled the incoming data at 2 samples per UI and at 1.45 samples per UI to achieve 5Gb/s and 6.875Gb/s, respectively. To further increase the data rate to 10Gb/s, we sample at baud rate (1 sample per UI). Existing baud-rate architectures [3] rely on a phase-tracking clock to sample at the middle of the data eye. This paper presents a blind baud-rate CDR, fabricated in 65nm CMOS. At 10Gb/s, the CDR demonstrates a high-frequency jitter tolerance of 0.19UI with ±300ppm of frequency offset. Also, the CDR demonstrates successful operation with 1000ppm offset, which amounts to sub-baud-rate sampling. Figure 7.4.1 illustrates the main challenge in the blind baud-rate sampling approach. Given an ideal channel, the data eye is open when sampled with a phase range spanning 1UI. However, with blind sampling, frequency offset between the data and receiver clock will cause the baud-rate sampling phase to shift continuously across a 1UI window. When the sampling occurs near the boundary, any high-frequency jitter may shift the sampling outside the 1UI phase range, resulting in the loss of data bits (i.e., zero jitter tolerance). To increase jitter tolerance, we introduce a controlled amount of ISI in the data by using a rectangular filter implemented as an integrate-and-dump (I&D) circuit [4] in the receiver front end. A 1UI rectangular filter, convolved with the ideal channel, spreads the pulse response to 2UI. If we have a perfect DFE to cancel all postcursor ISI, then the eye would be open for a range of 1.5UI. If the blind samples shift beyond the 1UI window, there is still a remaining jitter margin of 0.5UI pp . A 2UI rectangular filter increases this margin to 1UIpp and results in a symmetric eye opening with respect to the blind sampling window. For these reasons, we choose a 2UI I&D circuit in our design. The front end consists of four interleaved I&D and ADC blocks, each operating at 2.5GS/s. The I&D circuit integrates over 1UI intervals and samples the result, which the ADC converts into 5b digital values that are demuxed into 16 parallel samples. The digital CDR adds adjacent 5b 1UI I&D samples to synthesize 6b 2UI I&D samples. Since our ADC resolution is limited to 5 bits, if we were to obtain 2UI I&D samples directly in the analog domain and feed them to the ADC, we would have lost the added resolution.The digital CDR contains a feedback loop including a data interpolator, a speculative 2-tap DFE, a speculative Mueller-Muller phase detector (MMPD), and a conventional 2 nd -order loop filter. The data interpolator estimates the desired sample at the average interpolation phase (ϕ avg ) by linearly combining neighbouring blind samples. Given a negative frequency offset (i.e., data ...

Design metrics for blind ADC-based wireline receivers

“…A Mueller-Muller PD is used to estimate the phase, and a speculative 2-tap DFE is used to recover the bits. The measurement results provided in [4] confirm phase and data recovery operation with a highfrequency jitter tolerance of about 0.2UIpp even in the face of a 1000ppm of frequency offset, i.e. when the blind clock at the receiver samples the incoming signal at below the baud rate.…”

“…Fig. 3 shows the block diagrams of two architectures for a blind ADC-based CDR: the feed-forward architecture [3] and the DI-based architecture [4]. In both architectures, the sampling clock of the ADC is blind; i.e.…”

“…However, when the ADC clock is blind, it is possible that the received signal is sampled directly on its zero crossings, and the data is lost completely (since there is only one sample per UI). Yet, by using an integrate and dump filter [5] in the analog domain prior to the ADC, Ting et al [4] introduce intentional ISI in the data stream such that each bit is spilled over the adjacent bits. As a result, the data is contained not only in the center of the eye but also at zero crossings, and this makes 1x blind baud-rate CDR possible.…”

ADC-Based Backplane Receivers: Motivations, Issues and Future

“…As the ever-growing demands for higher data rate call for more sophisticated equalization schemes and the advances in fabrication technology favor digital circuit implementation, backplane receivers that rely on a frontend analog-to-digital converter (ADC) and a digital equalizer are gaining more popularity in these years [1][2][3][4][5][6][7][8]. Such ADC-based receivers not only provide opportunity to utilize advanced digital signal processing (DSP) techniques to perform higher-level of equalization, but also enable more robust circuit implementation against process variation, leakage, and noise.…”

A 3x blind ADC-based CDR

“…Blind ADC-based CDRs simplify the design and simulation of ADC-based CDRs by removing the feedback from the digital CDR to the analog ADC [1]- [4]. As shown in Fig.…”