A built-in technique for probing power supply and ground noise distribution within large-scale digital integrated circuits

Nagata, Makoto; Okumoto, Takeshi; Taki, Kazuo

doi:10.1109/jssc.2005.845559

Cited by 80 publications

(28 citation statements)

References 9 publications

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“…The p-substrate makes V ss voltage stable because the V ss current is widely diffused and drained to the system ground through the resistive network of the p-substrate in addition to supply wires. In previous published works, [3], [4] referred to the relation between the p-substrate and supply noise, [5] measured smaller V ss noise than V dd noise in a twinwell structure, and our preliminary work [6] measured noise reduction by a p-substrate.…”

Section: Introductionmentioning

confidence: 73%

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Supply Noise Suppression by Triple-Well Structure

Ogasahara

Hashimoto

Kanamoto

et al. 2013

IEEE Trans. VLSI Syst.

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Abstract-This brief discusses the impact of twin-and triplewell structures on power supply noise, and a substrate model for simulating the power supply noise. We observed V ss noise reduction by the resistive network of the p-substrate and V dd noise reduction by the junction capacitance of a triple-well structure on a 90-nm test chip. Measurement results also showed that the total noise reduction of a triple-well structure is superior to that of a twin-well structure. The measurement results correlate well with the results obtained from the power supply noise simulation using a hierarchical resistive mesh model. Our simulation-based verification indicates that in common CMOS design, a triplewell structure can reduce the power supply drop by 10%-40% or the decoupling capacitance area by 5%-10%. We also verified that supply drop sensitivity to variation of the well junction capacitance is sufficiently small and that supply noise reduction using a triple-well structure is robust to process variation.Index Terms-Circuit noise, noise measurement, substrate.

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Section: Introductionmentioning

confidence: 73%

“…Due to the resistive substrate network, the impedance of the V ss network becomes smaller, which helps to reduce V ss noise. Simulated and measured results for this V ss noise suppression were reported in [5].…”

Section: Introductionmentioning

confidence: 99%

Supply Noise Suppression by Triple-Well Structure

Ogasahara

Hashimoto

Kanamoto

et al. 2013

IEEE Trans. VLSI Syst.

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“…3. These single stage amplifier circuits utilize an array structured noise detection circuit, as suggested in [13]. Each device plane contains both power and ground noise detection circuits.…”

Section: B 3-d Circuit Architecturementioning

confidence: 99%

Power Noise in TSV-Based 3-D Integrated Circuits

Savidis

Köse

Friedman

2013

IEEE J. Solid-State Circuits

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“…Configuration included 2X-size inverters and 1X-size transmission gates, and was the smallest implementation. The layout size of was 10.08 6.72 m, which is similar or even smaller to the size of the other analog measurement circuits [4], [19].…”

Section: Implementation Of Test Chipsmentioning

confidence: 99%

All-Digital Ring-Oscillator-Based Macro for Sensing Dynamic Supply Noise Waveform

Ogasahara

Hashimoto

Onoye

2009

IEEE J. Solid-State Circuits

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Abstract-This paper proposes an all-digital measurement circuit called a "gated oscillator" to capture the waveforms of dynamic power supply noise. An improved gated oscillator with a power-gating structure is also proposed. The gated oscillator is constructed using standard cells, and thus is easily embedded in SoCs. Its performance was evaluated using test chips fabricated in a 90 nm process. The gated oscillator achieved 5.3-5.9 Gsample/s with an area of 10.08 6.72 m 2 , and the improved power gating structure achieved 6.6-8.3 Gsample/s in a 90 nm process. The characteristics of the gated oscillator and related design issues are also discussed. These characteristics were verified on silicon. We evaluated the effect of the decoupling capacitance based on measurement results obtained using the gated oscillator, and demonstrated that it could be used to verify power integrity.

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A built-in technique for probing power supply and ground noise distribution within large-scale digital integrated circuits

Cited by 80 publications

References 9 publications

Supply Noise Suppression by Triple-Well Structure

Supply Noise Suppression by Triple-Well Structure

Power Noise in TSV-Based 3-D Integrated Circuits

All-Digital Ring-Oscillator-Based Macro for Sensing Dynamic Supply Noise Waveform

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