A built-in test circuit for supply current testing of open defects at interconnects in 3D ICs

A Design for Testability of Open Defects at Interconnects in 3D Stacked ICs

“…However, modification of input protection circuits may not be acceptable in real designs. Thus, another DfT method was proposed by which input protection circuits were not modified [17], [18]. Since only an nMOS is added to each input interconnect by the DfT method, the area overhead is smaller than that for the method proposed in [15].…”

“…The test method proposed in [17] is based on measuring a quiescent supply current of an IC under test. Generally speaking, current measurements typically result in a higher test cost than measurements based on voltages, since a relatively expensive equipment is needed to measure currents.…”

“…Whenever an IC designed by the DfT method proposed in [17], [18] is tested, some part of the quiescent supply current may flow through interconnects other than the targeted one. This additional current reduces the sensitivity of open defect detection and it also necessitates the preparation of many threshold values for the tests prior to testing, since such thresholds depend on the number of the interconnects through which the supply current flows.…”

“…In case of dies designed by the DfT method proposed in [17], [18], I Dt is divided into I Dt1 and I Dt2 . As I Dt2 increases, the change in V Rc caused by an open defect decreases.…”

A built-in supply current test circuit for electrical interconnect tests of 3D ICs

“…Since a hard open defect may generate a logical error [10] and also a timing error, a soft open defect should be detected before it becomes a hard one. Thus, we have proposed an electrical test method with which hard open defects and soft ones can be detected [14,15].We call the test approach "Electrical Test with Scan flip flops" (ET-Scan).…”