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A new high speed IDDQ test method is proposed. It is based on charge current for load capacitances of gates whose output logic values are changed from L to H by test input vector application. In this paper, the testability of the test method is examined for some process variations generated in CMOS IC production.

This paper presents a design-for-testability method for detecting delay faults. In order to observe the effect of small delay defects, we present modified boundary scan cells in which a time-to-digital converter (TDC) is embedded. In our boundary scan cells, flip-flops are utilized for both making a scan path and capturing circuit response. The architecture of the boundary scan design is proposed to detect delay from the other cores or chips or its interconnects. The basic operation of the design is evaluated by simulation and by experimental ICs. Experimental results show that the measurement of the transition delay can be achieved by the boundary scan design with the time-to-digital converter.