Supply current testing of open defects at interconnects in 3D Ics with IEEE 1149.1 architecture

Konishi, Tomoaki; Yotsuyanagi, Hiroyuki; Hashizume, Masaki

doi:10.1109/3dic.2012.6262968

Cited by 15 publications

(15 citation statements)

References 16 publications

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“…⃝ 2018 The Institute of Electronics, Information and Communication Engineers proposed in [14]. Thus, there are no extra circuits added by the DfT method and the area overhead is smaller compared to the ones proposed in [15].…”

Section: Copyright Cmentioning

confidence: 99%

“…Thus, there are no extra circuits added by the DfT method and the area overhead is smaller compared to the ones proposed in [15]. The input protection circuits can be modified so that currents, supplied from boundary scan flip flops, flow during the tests only [14]. However, modification of input protection circuits may not be acceptable in real designs.…”

Section: Copyright Cmentioning

confidence: 99%

“…Electrical test methods proposed in [14] and [15] are based on a quiescent current that is made to flow through an interconnect under test, called a "targeted interconnect" in this paper. Dies are typically designed so that no quiescent current can normally flow.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

A Design for Testability of Open Defects at Interconnects in 3D Stacked ICs

Ashikin

Hashizume

Yotsuyanagi

et al. 2018

IEICE Trans. Inf. & Syst.

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SUMMARY A design-for-testability method and an electrical interconnect test method are proposed to detect open defects occurring at interconnects among dies and input/output pins in 3D stacked ICs. As part of the design method, an nMOS and a diode are added to each input interconnect. The test method is based on measuring the quiescent current that is made to flow through an interconnect to be tested. The testability is examined both by SPICE simulation and by experimentation.

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Section: Copyright Cmentioning

confidence: 99%

Section: Copyright Cmentioning

confidence: 99%

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A Design for Testability of Open Defects at Interconnects in 3D Stacked ICs

Ashikin

Hashizume

Yotsuyanagi

et al. 2018

IEICE Trans. Inf. & Syst.

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“…Since a hard open defect may generate a logical error [10] and also a timing error, a soft open defect should be detected before it becomes a hard one. Thus, we have proposed an electrical test method with which hard open defects and soft ones can be detected [14,15].We call the test approach "Electrical Test with Scan flip flops" (ET-Scan).…”

Section: Introductionmentioning

confidence: 99%

“…The test method proposed in [14] requests us to design ESD input protection circuits inside a die so as to be tested by the test method. We had prototyped an IC embedding the ESD input protection circuits and shown feasibility of interconnect tests with the prototype IC by some experiments [14].…”

Section: Introductionmentioning

confidence: 99%

A built-in supply current test circuit for electrical interconnect tests of 3D ICs

Hashizume

Umezu

Yotsuyanagi

et al. 2014

2014 International 3D Systems Integration Conference (3DIC)

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In this paper, a built-in supply current test circuit is proposed to detect open defects occurring at interconnects between dies including an IEEE 1149.1 test circuit and locate the defective interconnects in a 3D IC. Feasibility of interconnect tests with the test circuit is examined by some experiments with a prototyping IC in which the test circuit is embedded and bySpice simulation. The simulation results show that a hard open defect, a capacitive open one of 10nF and a resistive open one of 1kΩ can be detected at a test speed of 1MHz per an interconnect.

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