A Bulk FinFET Unified-RAM (URAM) Cell for Multifunctioning NVM and Capacitorless 1T-DRAM

Gate-to-Source/Drain Nonoverlap Device for Soft-Program Immune Unified RAM (URAM)

“…3(c). Before the cell is allocated to the 1T-DRAM mode, V T is adjusted to 0.2 V by preprogramming of the NVM [1], [2]. As shown in Fig.…”

“…U NIFIED RAM (URAM) is a promising fusion memory for combining high-speed DRAM and nonvolatile memory (NVM) into a single memory transistor [1], [2]. Unlike the conventional 1T/1C DRAM, the DRAM mode of URAM uses a floating-body hysteresis effect, which enables the capacitorless 1T-DRAM [3].…”

“…Because an O/N/O gate dielectric is used in a partially depleted floating-body structure, the operation of the NVM and capacitorless 1T-DRAM can be realized in a single memory transistor. In the 1T-DRAM mode, unfortunately, impact ionization for programming can adversely affect the trapped charges in the O/N/O layer, giving rise to a soft-program issue [1], [2]. While a harsh impact ionization condition can provide a faster writing speed and wider sensing window for 1T-DRAM, increased hot-electron injection causes an undesired shift in the threshold voltage (V T ) after cyclic 1T-DRAM operations.…”

Optimizing the Readout Bias for the Capacitorless 1T Bulk FinFET RAM Cell

“…Originally, partially depleted silicon-on-insulator (SOI) devices were used to demonstrate the working principle [1]. Later on, more scalable devices were also shown [2]- [4], and in [5] and [6], a 1T-DRAM cell realized on a bulk substrate has also been demonstrated. In particular, bulk FinFET devices are of high interest because they are more scalable than planar bulk devices, have an extra degree of freedom (fin height) for increasing the charge storage area, and can be cointegrated with planar bulk devices and, at the same time, avoid the problem of heat dissipation, which is present in SOI FinFET devices.…”

One-transistor nonvolatile SRAM (ONSRAM) on silicon nanowire SONOS

“…A partially-depleted (PD) FinFET was reported to enhance 1T-DRAM performance [1,2]; however it imposes a constraint on further scaling due to the tradeoff relation between the sensing margin and immunity to short-channeleffects (SCEs), as shown in Fig. 1.…”