Sub-5nm all-around gate FinFETs with 3nm fin width were fabricated for the first time. The n-channel FinFET of sub-5nm with 1.4nm HfO 2 shows an I Dsat of 497µA/µm at V G =V D =1.0V. Characteristics of sub-5nm transistor are verified by using 3-D simulations as well as analytical models. A threshold voltage increases as the fin width reduces by quantum confinement effects. The threshold voltage shift was fitted to a theoretical model with consideration of the first-order perturbation theory. And a channel orientation effect, based on a current-flow direction, is shown. Key words: all-around gate, FinFET, sub-5nm, quantum effect Introduction Silicon-based transistors are scaled down continually in order to increase a density and speed. Multi-gate FinFETs have strengths of high robustness on short-channel effects (SCEs) and superior scalability using conventional processes [1][2][3][4][5][6][7]. However, the ultimate minimum feature-sized device operating at room temperature has been expected to be 1.5nm according to Heisenberg's uncertainty principle and Shannon-von NeumannLandauer expression [8]. The fabricated sub-5nm all-around gate (AAG) FinFET is approaching to this fundamental limit. FinFET [7]. For ultimately scaled transistor, AAG FinFET is known to be the best structure to provide scalability and flexibility in device design [9]. This work primarily focuses on feasibility and scalability of sub-5nm AAG FinFET. A threshold voltage shift by quantum confinement and an effect of current-flow direction are reported.Fabrications Fig. 1 illustrates a process flow of AAG FinFET. As a starting material, (100) SOI wafers were used. 100nm silicon film was thinned down to 14nm by using thermal oxidations and HF wet etch. Dual-resist process for a fin and a gate patterning was used to define nanometer features by e-beam lithography and non-critical large-area patterns by optical lithography. After the silicon-fin etch, a sacrificial oxide was grown and removed to alleviate etching damages. Gate dielectrics were split into 1.4nm HfO 2 by atomic layer deposition and 2nm thermal SiO 2 . Reasonable characteristics of sub-5nm devices were achieved in HfO 2 group. 30nm in-situ n + poly-silicon was deposited for the gate electrode. The gate was patterned by the dual-resist process, similarly. After the gate and spacer formation, arsenic ions were implanted to form the source and drain (S/D). 1000℃ spike annealing was utilized to activate the dopants of S/D. Finally, forming gas annealing at 450℃ was applied. Metallization was skipped for iterative annealing to optimize gate-to-S/D overlap. The fabricated device dimensions are sub-5nm gate length (L G ), averaged 3nm fin width (W Fin ), and 14nm fin height (H Fin ).Results and Discussions Fig. 2 shows a SEM top-view of 3nm silicon-fin and sub-5nm gate. Fig. 3 and Fig. 4 show TEM cross-sectional views of 3nm silicon-fin (a-a' direction of Fig. 6 and Fig. 7. An on-state current is 497µA/µm at V G =V D =1.0V in Fig. 6, which is normalized by allarounded channel perime...

Free electron concentration and carrier mobility measurements on 4H–SiC metal-oxide-semiconductor inversion layers are reported in this article. The key finding is that in state-of-the-art nitrided gate oxides, loss of carriers by trapping no longer plays a significant role in the current degradation under heavy inversion conditions. Rather, it is the low carrier mobility (maximum∼60 cm2 V−1 s−1) that limits the channel current. The measured free carrier concentration is modeled using the charge-sheet model and the mobility is modeled by existing mobility models. Possible mobility mechanisms have been discussed based on the modeling results.

We report the synthesis of free-standing MnSi nanowires via a vapor transport method with no catalyst and measurements of their electrical and magnetic properties for the first time. The single-crystalline MnSi nanowire ensemble with a simple cubic (B20) crystal structure shows itinerant helimagnetic properties with a T(c) of about 30 K. A single MnSi nanowire device was fabricated by a new method using photolithography and a nanomanipulator that produces good ohmic contacts. The single-nanowire device measurements provide large (20%) negative magnetoresistance and very low electrical resistivity of 544 microOmegacm for the MnSi nanowire.

A nonvolatile memory is demonstrated using a solution-processed sol-gel ZnO thin-film transistor ͑TFT͒ in which Ag nanoparticles are embedded as charge storage nodes at the insulator-ZnO interface. Its TFT transfer characteristics exhibit a large clockwise hysteresis that is proportional to the gate bias sweep range. Measurement of the threshold voltage shift versus the pulse width of gate bias reveals that the device can be programed or erased at a time scale of as short as 10 −4 s. Retention of the initial memory window is measured to be 27% after 10 5 s and projected to last until 10 7 s.

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