A Cascaded Gate Driver Architecture to Increase the Switching Speed of Power Devices in Series Connection

Abstract

This paper presents a novel packaging technique to improve the voltage sharing performances of series-connected SiC-MOSFETs. The proposed method takes advantage of the parasitic capacitance network introduced by the packaging dielectric isolation layers in order to reduce the voltage unbalancing across the series-connected devices. In a first step, the study carried out in this work explains how the parasitic capacitance networks introduced by the classic planar packaging and the gate drive circuits unbalance the voltages across the devices. Therefore, a new packaging concept is proposed in order to compensate the effects of the gate driver parasitic capacitances. The concept is introduced and analyzed thanks to equivalent models and time domain simulations. To verify the analysis, the voltage sharing between two series-connected 1.2 kV SiC-MOSFETs is tested in a pulse test setup. The experimental results confirm that the proposed voltage balancing technique can drastically improve the voltage sharing performance.

An enhanced single gate driven voltage‐balanced SiC MOSFET stack topology suitable for high‐voltage low‐power applications

“…fibre isolation are needed [4]. Although the gate loops are designed to be identical, voltage unbalancing still occurs.…”

“…As mentioned, in the conventional way T i ( i = 1–4) in the stack requires an independent driving pulse, which means four groups of isolated power supply and driving chip with optic fibre isolation are needed [4]. Although the gate loops are designed to be identical, voltage unbalancing still occurs.…”

“…In the conventional way, as shown in the lower right part of Figure 1, each SiC MOSFET in the stack requires an independent driving voltage pulse [4]. Since the gate loops and power loops of devices are not identical caused by the difference of device parasitic parameters and driving pulses, a natural voltage unbalancing exists [5].…”